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參數(shù)資料
| 型號： | AD7703AR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 20BIT LC2MOS MONO 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 4k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 37mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
REV. E
AD7703
–3–
Parameter
A/S Version
2
B Version
2
C Version
2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
DC Power Supply Currents
8
Analog Positive Supply (AIDD)
2.7
mA max
Typically 2 mA
Digital Positive Supply (DIDD)2
22
mA max
Typically 1 mA
Analog Negative Supply (AISS)
2.7
mA max
Typically 2 mA
Digital Negative Supply (DISS)
0.1
mA max
Typically 0.03 mA
Power Supply Rejection
9
Positive Supplies
70
dB typ
Negative Supplies
75
dB typ
Power Dissipation
Normal Operation
37
mW max
SLEEP = Logic 1,
Typically 25 mW
Standby Operations
10
SLEEP = Logic 0,
A, B, C
20
W max
Typically 10
W
S40
40
W max
NOTES
1 The A
IN pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the AIN pin to AGND is necessary.
Source resistance should be 750
or less.
2 Temperature ranges are as follows: A, B, C Versions: –40
°C to +85°C; S Version: –55°C to +125°C.
3 Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4 Total drift over the specified temperature range after calibration at power-up at 25
°C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
5 In Unipolar mode, the offset can have a negative value (–V
REF) such that the Unipolar mode can mimic Bipolar mode operation.
6 The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7 For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale
points. When using less than the maximum input span, the span range may be placed anywhere within the range of
±(V
REF + 0.1).
8 All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9 Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10 CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(TA = 25
°C, unless otherwise noted.)
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . AVSS – 0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies
2 . . . . . . . .
±10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40
°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55
°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300
°C
Power Dissipation (DIP Package) to 75
°C . . . . . . . . . 450 mW
Derates above 75
°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Power Dissipation (SOIC Package) to 75
°C . . . . . . . 250 mW
Derates above 75
°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Linearity
Temperature
Error
Package
Model
Range
(% FSR)
Options
*
AD7703AN
–40
°C to +85°C
0.003
N-20
AD7703BN
–40
°C to +85°C
0.0015
N-20
AD7703CN
–40
°C to +85°C
0.0012
N-20
AD7703AR
–40
°C to +85°C
0.003
R-20
AD7703BR
–40
°C to +85°C
0.0015
R-20
AD7703CR
–40
°C to +85°C
0.0012
R-20
AD7703AQ
–40
°C to +85°C
0.003
Q-20
AD7703BQ
–40
°C to +85°C
0.0015
Q-20
AD7703CQ
–40
°C to +85°C
0.0012
Q-20
AD7703SQ
–55
°C to +125°C
0.003
Q-20
*N = Plastic DIP; R = SOIC; Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
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