參數(shù)資料
型號(hào)： AD7703CR-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 20BIT LC2MOS MONO 20-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 20
采樣率（每秒）： 4k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 37mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極
REV. E
AD7703
–15–
Synchronous External Clock Mode (SEC)
The SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry-standard
microprocessors such as the 68HC11 and 68HC05. The SEC
mode also allows customized interfaces, using I/O port pins, to
microprocessors that do not have a direct fit with the AD7703’s
other mode.
As shown in Figure 17, a falling edge on
CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK. After
the LSB has been transmitted,
DRDY and SDATA go three-state.
If
CS is low and the AD7703 is still transmitting data when a
new data-word becomes available, the old data-word continues
to be transmitted and the new data is lost.
If
CS is taken high at any time during data transmission, SDATA
will go three-state immediately. If
CS returns low, the AD7703
will continue transmission with the same data bit. If transmis-
sion has not been initiated and completed by the time the next
data-word becomes available, and if
CS is high, DRDY returns
high for four clock cycles, then falls as the new word is loaded
into the output register.
DIGITAL NOISE AND OUTPUT LOADING
As mentioned earlier, the AD7703 divides its internal timing
into two distinct phases, analog sampling and settling and digi-
tal computation. In the SSC mode, data is transmitted only
during the digital computation periods, to minimize the effects
of digital noise on analog performance. In the SEC mode, data
transmission is externally controlled, so this automatic safeguard
does not exist. To compensate, synchronize the AD7703 to the
digital system clock via CLKIN when used in the SEC mode.
Whatever mode of operation is used, resistive and capacitive
loads on digital outputs should be minimized in order to reduce
crosstalk between analog and digital portions of the circuit. For
this reason, connection to low power CMOS logic such as one
of the 4000 series or 74C families is recommended.
DRDY (O)
SDATA (O)
DB19 (MSB)
DB18
DB2
DB1
DB0 (LSB)
HI-Z
SCLK (O)
HI-Z
CS (I)
DB17
Figure 17. Timing Diagram for SEC Mode
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