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參數(shù)資料
| 型號(hào)： | AD7705BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 2CH 16-SOIC T/R |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極；2 個(gè)差分，雙極 |
| 配用： | EVAL-AD7705EBZ-ND - BOARD EVALUATION FOR AD7705 |
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AD7705/AD7706
Rev. C | Page 30 of 44
POWER SUPPLIES
The AD7705/AD7706 operate with VDD power supplies between
2.7 V and 5.25 V. Although the latch-up performance of the
AD7705/AD7706 is good, it is important that power is applied to
the AD7705/AD7706 before signals are applied at the REF IN,
AIN, or logic input pins to avoid excessive currents. If this is not
possible, the current through these pins should be limited. If
separate supplies are used for the AD7705/AD7706 and the system
digital circuitry, the AD7705/AD7706 should be powered up first.
If it is not possible to guarantee this, current-limiting resistors
should be placed in series with the logic inputs to limit the
current. The latch-up current is greater than 100 mA.
SUPPLY CURRENT
The current consumption on the AD7705/AD7706 is specified
for supplies in the range of 2.7 V to 3.3 V and 4.75 V to 5.25 V.
The parts operate over a 2.7 V to 5.25 V supply range, and the
IDD changes as the supply voltage varies over this range. There is
an internal current boost bit on the AD7705/AD7706 that is set
internally in accordance with the operating conditions. This
affects the current drawn by the analog circuitry within these
devices. Minimum power consumption is achieved when the
AD7705/AD7706 are operated with an fCLKIN of 1 MHz, or at
gains of 1 to 4 with fCLKIN = 2.4575 MHz, because the internal
boost bit reduces the analog current consumption. Figure 18
shows the variation of the typical IDD with VDD voltage for both a
1 MHz crystal oscillator and a 2.4576 MHz crystal oscillator at
25°C. The AD7705/AD7706 are operated in unbuffered mode.
The relationship shows that the IDD is minimized by operating
the part with lower VDD voltages. IDD on the AD7705/AD7706
is also minimized by using an external master clock, or by
optimizing external components when using the on-chip
show variations in IDD with gain, VDD, and clock frequency
using an external clock.
VDD
1600
0
I DD
(
μA)
1400
800
600
400
200
1200
1000
2.5
5.5
3.0
3.5
4.0
4.5
5.0
MCLK IN = CRYSTAL OSCILLATOR
TA = 25°C
UNBUFFERED MODE
GAIN = +128
fCLK = 2.4576MHz
fCLK = 1MHz
01166-018
Figure 18. IDD vs. Supply Voltage
GROUNDING AND LAYOUT
Because the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. The excellent common-mode rejection of the parts
removes common-mode noise on these inputs. The digital filter
provides rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital filter also removes noise from the analog and reference
inputs, provided that those noise sources do not saturate the
analog modulator. As a result, the AD7705/AD7706 are more
immune to noise interference than conventional high resolution
converters. However, because the resolutions of the AD7705/
AD7706 are so high and the noise levels from the AD7705/
AD7706 are so low, care must be taken with regard to grounding
and layout.
The printed circuit board that houses the AD7705/AD7706
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be separated easily.
A minimum etch technique is generally best for ground planes,
because it provides the best shielding. Digital and analog
ground planes should only be joined in one place to avoid
ground loops. If the AD7705/AD7706 are in a system where
multiple devices require AGND-to-DGND connections, the
AGND-to-DGND connection should only be made at one
point, a star ground point, which should be established as close
as possible to the AD7705/AD7706 GND.
Avoid running digital lines under the device, because they couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7705/AD7706 to avoid noise coupling. The
power supply lines to the AD7705/AD7706 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals,
such as clock signals, should be shielded with digital ground to
avoid radiating noise to other sections of the board, and clock
signals should never be run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. Using a
microstrip technique works best, but it is not always possible to
use this method with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
and signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. All analog supplies should be decoupled with 10 μF
tantalum in parallel with 0.1 μF ceramic capacitors to GND. To
achieve the best from these decoupling components, place them
as close as possible to the device, ideally right up against the
device. All logic chips should be decoupled with 0.1 μF disc
ceramic capacitors to DGND.
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