參數(shù)資料
型號(hào)： AD7706BNZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/44頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 3CHAN 16DIP
標(biāo)準(zhǔn)包裝： 25
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 16-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 16-PDIP
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)偽差分，單極; 3 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
配用： EVAL-AD7706EBZ-ND - BOARD EVALUATION FOR AD7706
AD7705/AD7706
Rev. C | Page 18 of 44
Table 16. Operating Mode Options
MD1
MD0
Operating Mode
0
Normal Mode. In this mode, the device performs normal conversions.
0
1
Self-Calibration. This activates self-calibration on the channel selected by CH1 and CH0 of the communication register. This
is a one-step calibration sequence. When the sequence is complete, the part returns to normal mode, with both MD1 and
MD0 returning to 0. The DRDY output or bit goes high when calibration is initiated, and returns low when self-calibration is
complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain
on internally shorted (zeroed) inputs, and the full-scale calibration is performed at the selected gain on an internally
generated VREF/selected gain.
1
0
Zero-Scale System Calibration. This activates zero-scale system calibration on the channel selected by CH1 and CH0 of the
communication register. Calibration is performed at the selected gain on the input voltage provided at the analog input
during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY
output or bit goes high when calibration is initiated, and returns low when zero-scale calibration is complete and a new
valid word is available in the data register. At the end of the calibration, the part returns to normal mode, with both MD1
and MD0 returning to 0.
1
Full-Scale System Calibration. This activates full-scale system calibration on the selected input channel. Calibration is
performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This
input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is
initiated, and returns low when full-scale calibration is complete and a new valid word is available in the data register. At the
end of the calibration, the part returns to normal mode, with both MD1 and MD0 returning to 0.
Table 17. Gain Selection
G2
G1
G0
Gain Setting
0
1
0
1
2
0
1
0
4
0
1
8
1
0
16
1
0
1
32
1
0
64
1
128
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