參數(shù)資料
型號(hào)： AD7711AAR
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
REV. D
AD7711A
–18–
System Offset Calibration
System offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System-offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full-
scale coefficient is determined from the span between this AIN
conversion and a conversion on VREF. The zero-scale point
should be applied to the AIN input for the duration of the cali-
bration sequence. This is a one-step calibration sequence with
DRDY going low when the sequence is completed. In the uni-
polar mode, the system offset calibration is performed between
the two endpoints of the transfer function; in the bipolar mode,
it is performed between midscale and positive full scale.
Background Calibration
The AD7711A also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
same voltages used as the calibration points in the self-calibra-
tion mode are used, i.e., shorted inputs and VREF. The back-
ground calibration mode is invoked by writing 1, 0, 1 to MD2,
MD1, MD0 of the control register. When invoked, the back-
ground calibration mode reduces the output data rate of the
AD7711A by a factor of 6 while the –3 dB bandwidth remains
unchanged. Its advantage is that the part is continually perform-
ing calibration and automatically updating its calibration coeffi-
cients. As a result, the effects of temperature drift, supply
sensitivity, and time drift on zero-scale and full-scale errors are
automatically removed. When the background calibration mode
is turned on, the part will remain in this mode until bits MD2,
MD1, and MD0 of the control register are changed. With back-
ground calibration mode on, the first result from the AD7711A
will be incorrect as the full-scale calibration will not have been
performed. For a step change on the input, the second output
update will have settled to 100% of the final value.
Table VI summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits on
the amount of offset and span that can be accommodated. The
range of input span in both the unipolar and bipolar modes has
a minimum value of 0.8
VREF/GAIN and a maximum value of
2.1
VREF/GAIN.
The amount of offset that can be accommodated depends on
whether the unipolar or bipolar mode is being used. This offset
range is limited by the requirement that the positive full-scale
calibration limit is
1.05 VREF/GAIN. Therefore, the offset
range plus the span range cannot exceed 1.05
VREF/GAIN. If
the span is at its minimum (0.8
VREF/GAIN), the maximum
the offset can be is (0.25
VREF/GAIN).
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (i.e., AIN(+) = AIN(–) = VBIAS) and
the full-scale point is VREF. The zero-scale coefficient is deter-
mined by converting an internal shorted inputs node. The
full-scale coefficient is determined by the span between this
shorted inputs conversion and a conversion on an internal VREF
node. The self-calibration mode is invoked by writing the appro-
priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the
control register. In this calibration mode, the shorted inputs
node is switched in to the modulator first and a conversion is
performed; the VREF node is then switched in and another con-
version is performed. When the calibration sequence is com-
plete, the calibration coefficients updated and the filter resettled
to the analog input voltage, the
DRDY output goes low. The
self-calibration procedure takes into account the selected gain
on the PGA.
For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that just outlined. In this case, the
two points that the AD7711A calibrates are midscale (bipolar
zero) and positive full scale.
System Calibration
System calibration allows the AD7711A to compensate for
system gain and offset errors as well as its own internal errors.
System calibration performs the same slope factor calculations
as self-calibration but uses voltage values presented by the sys-
tem to the AIN inputs for the zero-scale and full-scale points.
System calibration is a two-step process. The zero-scale point
must be presented to the converter first. It must be applied to
the converter before the calibration step is initiated and remain
stable until the step is complete. System calibration is initiated
by writing the appropriate values (0, 1, 0) to the MD2, MD1,
and MD0 bits of the control register. The
DRDY output from
the device will signal when the step is complete by going low.
After the zero-scale point is calibrated, the full-scale point is
applied, and the second step of the calibration process is initi-
ated by again writing the appropriate values (0, 1, 1) to MD2,
MD1, and MD0. Again the full-scale voltage must be set up
before the calibration is initiated, and it must remain stable
throughout the calibration step.
DRDY goes low at the end of
this second step to indicate that the system calibration is com-
plete. In the unipolar mode, the system calibration is performed
between the two endpoints of the transfer function; in the bipolar
mode, it is performed between midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from what was
set during a full system calibration sequence.
System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti-
aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.
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