參數(shù)資料
型號: AD7711AQ
廠商: Analog Devices Inc
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC ADC 24BIT RTD I SOURCE 24CDIP
標(biāo)準(zhǔn)包裝: 15
位數(shù): 24
采樣率(每秒): 1.03k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 52.5mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 80°C
安裝類型: 通孔
封裝/外殼: 24-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-CDIP
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極;1 個單端,雙極;1 個差分,單極;1 個差分,雙極
2
REV.G
AD7711
–19–
Measurement errors due to offset drift or gain drift can be elimi-
nated at any time by recalibrating the converter or by operating
the part in the background calibration mode. Using the system
calibration mode can also minimize offset and gain errors in the
signal conditioning circuitry. Integral and differential linearity
errors are not significantly affected by temperature changes.
POWER SUPPLIES AND GROUNDING
Because the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. VBIAS provides the return path for most of the analog
currents flowing in the analog modulator. As a result, the VBIAS
input should be driven from a low impedance to minimize errors
due to charging/discharging impedances on this line. When the
internal reference is used as the reference source for the part,
AGND is the ground return for this reference voltage.
The analog and digital supplies to the AD7711 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The digital filter will
provide rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital supply (DVDD) must not exceed the analog positive
supply (AVDD) by more than 0.3 V in normal operation. If separate
analog and digital supplies are used, the recommended decoupling
scheme is shown in Figure 9. In systems where AVDD = 5 V and
DVDD = 5 V, it is recommended that AVDD and DVDD are
driven from the same 5 V supply, although each supply should be
decoupled separately as shown in Figure 9. It is preferable that
the common supply is the system’s analog 5 V supply.
It is also important that power is applied to the AD7711 before
signals at REF IN, AIN, or the logic input pins in order to avoid
latch-up. If separate supplies are used for the AD7711 and the
system digital circuitry, the AD7711 should be powered up first.
If it is not possible to guarantee this, current limiting resistors
should be placed in series with the logic inputs.
AD7711
AVDD
DVDD
0.1 F
10 F
ANALOG
SUPPLY
0.1 F
DIGITAL 5V
SUPPLY
Figure 9. Recommended Decoupling Scheme
DIGITAL INTERFACE
The AD7711’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers, and digital signal processors.
A serial read to the AD7711 can access data from the output
register, the control register, or the calibration registers. A serial
write to the AD7711 can write data to the control register or the
calibration registers.
Two different modes of operation are available, optimized for
different types of interfaces where the AD7711 can act either as
master in the system (it provides the serial clock) or as slave (an
external serial clock can be provided to the AD7711). These
two modes, labelled self-clocking mode and external clocking
mode, are discussed in detail in the following sections.
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