參數(shù)資料
型號(hào)： AD7711ARZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 80°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
2
REV.G
AD7711
–13–
microprocessor much greater control over the AD7711’s cali-
bration procedure. It also means that the user can verify the
calibration is correct by comparing the coefficients after calibra-
tion with prestored values in E
2PROM.
The AD7711 can be operated in single-supply systems provided
that the analog input voltage does not go more negative than
–30 mV. For larger bipolar signals, a VSS of –5 V is required by
the part. For battery operation, the AD7711 also offers a pro-
grammable standby mode that reduces idle power consumption
to typically 7 mW.
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:
∑ A sample-hold amplifier.
∑ A differential amplifier or subtracter.
∑ An analog low-pass filter.
∑ A 1-bit A/D converter (comparator).
∑ A 1-bit DAC.
∑ A digital low-pass filter.
ANALOG
LOW-PASS
FILTER
DIGITAL
FILTER
DIGITAL
DATA
+
–
S/H AMP
DAC
COMPARATOR
Figure 4. General Sigma-Delta ADC
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, which samples the difference
signal at a frequency many times that of the analog signal sampling
frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC,
SNR = (6.02
number of bits + 1.76) dB,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7711 samples the input signal at a frequency of 39 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor-
mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figure 2.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data-word using a
digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order sigma-
delta ADC is shown in Figure 5. This contains only a first-order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices, charge-balancing ADCs.
DAC
COMPARATOR
+FS
–FS
INTEGRATOR
DIFFERENTIAL
AMPLIFIER
VIN
Figure 5. Basic Charge-Balancing ADC
The device consists of a differential amplifier (whose output is
the difference between the analog input and the output of a
1-bit DAC), an integrator, and a comparator. The term charge-
balancing comes from the fact that this system is a negative
feedback loop that tries to keep the net charge on the integrator
capacitor at zero, by balancing charge injected by the input
voltage with charge injected by the 1-bit DAC. When the analog
input is zero, the only contribution to the integrator output
comes from the 1-bit DAC. For the net charge on the integrator
capacitor to be zero, the DAC output must spend half its time at
+FS and half its time at –FS. Assuming ideal components, the
duty cycle of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7711 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up, or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
Input Sample Rate
The modulator sample frequency for the device remains at
fCLK IN/512 (19.5 kHz @ fCLK IN = 10 MHz) regardless of the
selected gain. However, gains greater than
1 are achieved by a
combination of multiple input samples per modulator cycle and
scaling the ratio of reference capacitor to input capacitor. As a
result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The
effective input impedance is 1/C
fS where C is the input sam-
pling capacitance and fS is the input sample rate.
Table III. Input Sampling Frequency vs. Gain
Gain
Input Sampling Frequency (fS)
1fCLK IN/256 (39 kHz @ fCLK IN = 10 MHz)
22
fCLK IN/256 (78 kHz @ fCLK IN = 10 MHz)
44
fCLK IN/256 (156 kHz @ fCLK IN = 10 MHz)
88
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
16
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
32
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
64
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
128
8
fCLK IN/256 (312 kHz @ fCLK IN = 10 MHz)
DIGITAL FILTERING
The AD7711’s digital filter behaves like a similar analog filter,
with a few minor differences.
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