參數(shù)資料
型號(hào)： AD7712AN
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 12/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC SIGNAL COND LC2MOS 24-DIP
標(biāo)準(zhǔn)包裝： 15
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 45mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 24-PDIP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)差分，單極；1 個(gè)差分，雙極
REV. F
–2–
AD7712–SPECIFICATIONS
Parameter
A, S Versions
1
Unit
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
24
Bits min
Guaranteed by Design. For Filter Notches
≤ 60 Hz
22
Bits min
For Filter Notch = 100 Hz
18
Bits min
For Filter Notch = 250 Hz
15
Bits min
For Filter Notch = 500 Hz
12
Bits min
For Filter Notch = 1 kHz
Output Noise
See Tables I and II
Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ 25
°C
±0.0015
% FSR max
Filter Notches
≤ 60 Hz
TMIN to TMAX
±0.003
% FSR max
Typically
±0.0003%
Positive Full-Scale Error
2, 3, 4
Excluding Reference
Full-Scale Drift
5
1
V/°C typ
Excluding Reference. For Gains of 1, 2
0.3
V/°C typ
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2, 4
Unipolar Offset Drift
5
0.5
V/°C typ
For Gains of 1, 2
0.25
V/°C typ
For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2, 4
Bipolar Zero Drift
5
0.5
V/°C typ
For Gains of 1, 2
0.25
V/°C typ
For Gains of 4, 8, 16, 32, 64, 128
Gain Drift
2
ppm/
°C typ
Bipolar Negative Full-Scale Error
2 @ 25
°C
±0.003
% FSR max
Excluding Reference
TMIN to TMAX
±0.006
% FSR max
Typically
±0.0006%
Bipolar Negative Full-Scale Drift
5
1
V/°C typ
Excluding Reference. For Gains of 1, 2
0.3
V/°C typ
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Normal-Mode 50 Hz Rejection
6
100
dB min
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±0.02 f
NOTCH
Normal-Mode 60 Hz Rejection
6
100
dB min
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±0.02 fNOTCH
AIN1/REF IN
DC Input Leakage Current @ 25
°C6
10
pA max
TMIN to TMAX
1
nA max
Sampling Capacitance
6
20
pF max
Common-Mode Rejection (CMR)
100
dB min
At dc and AVDD = 5 V
90
dB min
At dc and AVDD = 10 V
Common-Mode 50 Hz Rejection
6
150
dB min
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±0.02 fNOTCH
Common-Mode 60 Hz Rejection
6
150
dB min
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±0.02 f
NOTCH
Common-Mode Voltage Range
7
VSS to AVDD
V min to V max
Analog Inputs
8
Input Sampling Rate, fS
See Table III
AIN1 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 V to VREF
10
V max
Unipolar Input Range (B/U Bit of Control Register = 1)
±V
REF
V max
Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 V to 4
VREF
10
V max
Unipolar Input Range (B/U Bit of Control Register = 1)
±4
VREF
V max
Bipolar Input Range (B/U Bit of Control Register = 0)
AIN2 DC Input Impedance
30
k
AIN2 Gain Error
11
±0.05
% typ
Additional Error Contributed by Resistor Attenuator
AIN2 Gain Drift
1
ppm/
°C typ
Additional Drift Contributed by Resistor Attenuator
AIN2 Offset Error
11
10
mV max
Additional Error Contributed by Resistor Attenuator
AIN2 Offset Drift
20
V/°C typ
Reference Inputs
REF IN(+) – REF IN(–) Voltage
12
2.5 to 5
V min to V max
For Specified Performance. Part Is Functional with
Lower VREF Voltages
Input Sampling Rate, fS
fCLK IN/256
NOTES
1Temperature range is as follows: A Version, –40
°C to +85°C; S Version –55°C to +125°C. See also Note 18.
2Applies after calibration at the temperature of interest.
3Positive full-scale error applies to both unipolar and bipolar input ranges.
4These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20
V typical after self-calibration
or background calibration.
5Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6These numbers are guaranteed by design and/or characterization.
7This common-mode voltage range is allowed, provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV
DD + 30 mV and VSS – 30 mV.
8The AIN1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).
9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV DD + 30 mV or more negative than VSS – 30 mV.
10V
REF = REF IN(+) – REF IN(–).
11This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the Static Performance section.
12The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS input.
(AVDD = +5 V
5%; DVDD = +5 V
5%; VSS = 0 V or –5 V
5%; REF IN(+) = +2.5 V;
REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.)
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