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參數(shù)資料
| 型號： | AD7712AR-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SGNL CONDTNR 24SOIC |
| 標準包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極；1 個差分，雙極 |
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REV. F
–18–
AD7712
The AD7712 also provides the facility to write to the on-chip
calibration registers, and, in this manner, the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value that is subtracted from all conversion
results, while the full-scale calibration register contains a value
that is multiplied by all conversion results. The offset calibration
coefficient is subtracted from the result prior to the multiplication
by the full-scale coefficient. In the first three modes outlined
here, the
DRDY line indicates that calibration is complete by
going low. If
DRDY is low before (or goes low during) the
calibration command, it may take up to one modulator cycle
before
DRDY goes high to indicate that calibration is in progress.
Therefore, the
DRDY line should be ignored for up to one
modulator cycle after the last bit of the calibration command is
written to the control register.
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (i.e., AIN1(+) = AIN1(–) = VBIAS
for AIN1 and AIN2 = VBIAS for AIN2 ) and the full-scale point
is VREF. The zero-scale coefficient is determined by converting
an internal shorted inputs node. The full-scale coefficient is
determined from the span between this shorted inputs conversion
and a conversion on an internal VREF node. The self-calibra-
tion mode is invoked by writing the appropriate values (0, 0, 1)
to the MD2, MD1, and MD0 bits of the control register. In this
calibration mode, the shorted inputs node is switched in to the
modulator first and a conversion is performed; the VREF node is
then switched in, and another conversion is performed. When
the calibration sequence is complete, the calibration coefficients
updated and the filter resettled to the analog input voltage, the
DRDY output goes low. The self-calibration procedure takes
into account the selected gain on the PGA.
For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that just outlined. In this case, the
two points that the AD7712 calibrates are midscale (bipolar
zero) and positive full scale.
System Calibration
System calibration allows the AD7712 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration but uses voltage values presented by the system to
the AIN inputs for the zero-scale and full-scale points. System
calibration is a two-step process. The zero-scale point must be
presented to the converter first. It must be applied to the con-
verter before the calibration step is initiated and remain stable
until the step is complete. System calibration is initiated by
writing the appropriate values (0, 1, 0) to the MD2, MD1, and
MD0 bits of the control register. The
DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied
and the second step of the calibration process is initiated by
again writing the appropriate values (0, 1, 1) to MD2, MD1,
and MD0. Again the full-scale voltage must be set up before the
calibration is initiated, and it must remain stable throughout the
calibration step.
DRDY goes low at the end of this second step
to indicate that the system calibration is complete. In the
unipolar mode, the system calibration is performed between the
two endpoints of the transfer function; in the bipolar mode, it is
performed between midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from what was
set during a full system calibration sequence.
System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti-
aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.
System Offset Calibration
System offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full-
scale coefficient is determined from the span between this AIN
conversion and a conversion on VREF. The zero-scale point
should be applied to the AIN input for the duration of the cali-
bration sequence. This is a one-step calibration sequence with
DRDY going low when the sequence is completed. In the uni-
polar mode, the system offset calibration is performed between
the two endpoints of the transfer function; in the bipolar mode,
it is performed between midscale and positive full scale.
Background Calibration
The AD7712 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
same voltages used as the calibration points in the self-calibration
mode are used, i.e., shorted inputs and VREF. The background
calibration mode is invoked by writing 1, 0, 1 to MD2, MD1,
MD0 of the control register. When invoked, the background
calibration mode reduces the output data rate of the AD7712 by
a factor of 6, while the –3 dB bandwidth remains unchanged. Its
advantage is that the part is continually performing calibration
and automatically updating its calibration coefficients. As a
result, the effects of temperature drift, supply sensitivity, and
time drift on zero-scale and full-scale errors are automatically
removed. When the background calibration mode is turned on,
the part will remain in this mode until bits MD2, MD1, and
MD0 of the control register are changed. With background
calibration mode on, the first result from the AD7712 will be
incorrect as the full-scale calibration will not have been per-
formed. For a step change on the input, the second output
update will have settled to 100% of the final value.
Table VI summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.
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| AD7712ARZ-REEL | 功能描述:IC ADC 24BIT SGNL CONDTNR 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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