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參數(shù)資料
| 型號(hào)： | AD7713ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 205 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 5.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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REV. D
AD7713
–21–
DRDY line will go high, turning off the SDATA output as per
Figure 12a.
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY line, and the write operation does not have any
effect on the status of
DRDY. A write operation to the control
register or the calibration register must always write 24 bits to
the respective register.
Figure 13a shows a write operation to the AD7713 with
TFS
remaining low for the duration of the write operation. A0
determines whether a write operation transfers data to the con-
trol register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7713
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7713 on the high level of this
SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7713.
Figure 13b shows a timing diagram for a write operation to the
AD7713 with
TFS returning high during the write operation
and returning low again to write the rest of the data-word. Tim-
ing parameters and functions are very similar to that outlined
for Figure 13a, but Figure 13b has a number of additional times
to show timing relationships when
TFS returns high in the
middle of transferring a word.
Data to be loaded to the AD7713 must be valid prior to the
rising edge of the SCLK signal.
TFS should return high during
the low time of SCLK. After
TFS returns low again, the next bit
of the data-word to be loaded to the AD7713 is clocked in on
the next high level of the SCLK input. On the last active high
time of the SCLK input, the LSB is loaded to the AD7713.
SIMPLIFYING THE EXTERNAL CLOCKING MODE
INTERFACE
In many applications, the user may not require the facility of
writing to the on-chip calibration registers. In this case, the
serial interface to the AD7713 in external clocking mode can be
simplified by connecting the
TFS line to the A0 input of the
AD7713 (see Figure 14). This means that any write to the
device will load data to the control register (since A0 is low
while
TFS is low), and any read to the device will access data
from the output data register or from the calibration registers
(since A0 is high while
RFS is low). It should be noted that in
this arrangement, the user does not have the capability of read-
ing from the control register. Another method of simplifying the
interface is to generate the
TFS signal from an inverted RFS
signal. However, generating the signals the opposite way around
(
RFS from an inverted TFS) will cause writing errors.
FOUR
INTERFACE
LINES
RFS
AD7713
SDATA
SCLK
TFS
A0
Figure 14. Simplified Interface with
TFS Connected to A0
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
LSB
t32
t33
t34
t26
t27
t36
t35
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
BIT N
BIT N+1
t32
t26
t30
t27
t36
t35
t36
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
(
TFS Returns High During Write Operation)
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