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    參數(shù)資料
    型號(hào)： AD7714ARS-5
    廠商： Analog Devices Inc
    文件頁(yè)數(shù)： 22/40頁(yè)
    文件大?。?/td> 0K
    描述： IC ADC SIGNAL COND 5V 28-SSOP
    標(biāo)準(zhǔn)包裝： 1
    位數(shù)： 24
    采樣率（每秒）： 1k
    數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
    轉(zhuǎn)換器數(shù)目： 1
    功率耗散（最大）： 7mW
    電壓電源： 模擬和數(shù)字
    工作溫度： -40°C ~ 85°C
    安裝類型： 表面貼裝
    封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
    供應(yīng)商設(shè)備封裝： 28-SSOP
    包裝： 管件
    輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
    配用： EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
    2
    AD7714
    REV. C
    –29–
    DIGITAL INTERFACE
    The AD7714’s programmable functions are controlled using a
    set of on-chip registers as previously outlined. Data is written to
    these registers via the part’s serial interface, and read access to
    the on-chip registers is also provided by this interface. All com-
    munications to the part must start with a write operation to the
    Communications Register. After power-on or
    RESET, the de-
    vice expects a write to its Communications Register. The data
    written to this register determines whether the next operation to
    the part is a read or a write operation and also determines to
    which register this read or write operation occurs. Therefore,
    write access to any of the other registers on the part starts with a
    write operation to the Communications Register followed by a
    write to the selected register. A read operation from any register
    on the part (including the output data register) starts with a
    write operation to the Communications Register followed by a
    read operation from the selected register.
    The AD7714’s serial interface consists of five signals,
    CS,
    SCLK, DIN, DOUT and
    DRDY. The DIN line is used for
    transferring data into the on-chip registers while the DOUT line
    is used for accessing data from the on-chip registers. SCLK is
    the serial clock input for the device and all data transfers (either
    on DIN or DOUT) take place with respect to this SCLK signal.
    The
    DRDY line is used as a status signal to indicate when data
    is ready to be read from the AD7714’s data register.
    DRDY
    goes low when a new data word is available in the output regis-
    ter. It is reset high when a read operation from the data register
    is complete. It also goes high prior to the updating of the output
    register to indicate when not to read from the device to ensure
    that a data read is not attempted while the register is being
    updated.
    CS is used to select the device. It can be used to de-
    code the AD7714 in systems where a number of parts are con-
    nected to the serial bus.
    The AD7714 serial interface can operate in three-wire mode by
    tying the
    CS input low. In this case, the SCLK, DIN and
    DOUT lines are used to communicate with the AD7714 and
    the status of
    DRDY can be obtained by interrogating the MSB
    of the Communications Register.
    Figures 6 and 7 show timing diagrams for interfacing to the
    AD7714 with
    CS used to decode the part. Figure 6 is for a read
    operation from the AD7714’s output shift register, while Figure
    7 shows a write operation to the input shift register. Both dia-
    grams are for the POL input at a logic high; for operation with
    the POL input at a logic low simply invert the SCLK waveform
    shown in the diagrams. It is possible to read the same data
    twice from the output register even though the
    DRDY line
    returns high after the first read operation. Care must be taken,
    however, to ensure that the read operations have been com-
    pleted before the next output update is about to take place.
    The serial interface can be reset by exercising the
    RESET input
    on the part. It can also be reset by writing a series of 1s on the
    DIN input. If a logic 1 is written to the AD7714 DIN line for at
    least 32 serial clock cycles the serial interface is reset. This
    ensures in three-wire systems that if the interface gets lost, either
    via a software error or by some glitch in the system, it can be
    reset back into a known state. This state returns the interface to
    where the AD7714 is expecting a write operation to the Com-
    munications Register. This operation does not in itself reset the
    contents of any registers but since the interface was lost, the
    information that was written to any of the registers is unknown
    and it is advisable to set up all registers again.
    Figure 6. Read Cycle Timing Diagram (POL = 1)
    Figure 7. Write Cycle Timing Diagram (POL = 1)
    DOUT
    SCLK
    CS
    DRDY
    MSB
    t5
    t7
    t9
    LSB
    t8
    t6
    t4
    t3
    t10
    DIN
    SCLK
    CS
    MSB
    t12
    t15
    LSB
    t16
    t14
    t11
    t13
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