參數(shù)資料
型號(hào)： AD7729ARZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 15BIT DUAL W/DAC 28SOIC
標(biāo)準(zhǔn)包裝： 27
類型： ADC，DAC
分辨率（位）： 15 b
采樣率（每秒）： 270.8k
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 管件
AD7729
–13–
REV. 0
Table IV. Baseband and Auxiliary Registers
Name
R/W
Address
Reset
Reserved
000000 (0)
Reserved
000001 (1)
Reserved
000010 (2)
IRxOFFSET
R/W
000011 (3)
BRESET
QRxOFFSET
R/W
000100 (4)
BRESET
Reserved
000101 (5)
Reserved
000110 (6)
RxDELAY1
R/W
000111 (7)
BRESET
RxDELAY2
R/W
001000 (8)
BRESET
ARDADDR
R/W
001001 (9)
SRESET
BRDADDR
R/W
001010 (10)
SRESET
Reserved
001011 (11)
AUXDAC
R/W
001100 (12)
ARESET
Reserved
001101 (13)
Reserved
001110 (14)
Reserved
001111 (15)
Reserved
010000 (16)
Reserved
010001 (17)
ACRA
R/W
010010 (18)
ARESET
ACRB
R/W
010011 (19)
ARESET
BCRA
R/W
010100 (20)
BRESET
BCRB
R/W
010101 (21)
BRESET
Reserved
010110 (22)
Reserved
010111 (23)
Reserved
011000 (24)
ASCLKRATE
R/W
011001 (25)
SRESET
BSCLKRATE
R/W
011010 (26)
SRESET
BRESET: can be reset using pin RESETB or bit BRESET.
ARESET: can be reset using pin RESETB or bit ARESET.
SRESET: only the pin RESETB can reset these registers.
Table V. Baseband Control Register A (BCRA)
Bit
Name
Function
BCRA0
MCLKDIV
MCLK Divider. When this bit is
set to 0, the internal MCLK has
the same value as the external
MCLK. When this bit equals 1,
the external MCLK is divided by
2 within the AD7729 so that the
device operates at half the exter-
nal clock frequency.
BCRA1
RxAUTOCAL
Selects AutoCal when set to 1
and UserCal when set to 0.
BCRA2
RxEXTCAL
When set to 1, the Rx calibration
operates in external mode i.e.,
the I and Q analog inputs remain
connected to the pins during the
Rx autocalibration routine.
BCRA3
RxPOWER0
This bit, in conjunction with
RxPOWER1, is used to reduce
the analog current consumption
of the ADCs.
BCRA4
RxPOWER1
This bit, in conjunction with
RxPOWER0, is used to reduce
the analog current consumption
of the ADCs.
BCRA5
Reserved
BCRA6
RxON
Power-on for the receive section
of the AD7729.
BCRA7
BRESET
Baseband Reset.
BCRA8
Reserved
BCRA9
Reserved
Table VI. Power Modes for the ADCs
RxPOWER1
RxPOWER0
AIDD1 Reduction
0
Reserved
0
1
1/3 (Power Mode 1)
1
0
2/5 (Power Mode 2)
1
Reserved
Bits RxPOWER0 and RxPOWER1 are used to reduce the ana-
log current consumption of the ADCs. The part is specified in
Power Mode 1. In Power Mode 2, the MCLK needs to be less
than 10 MHz. The performance of the part will then be compa-
rable to the performance in Power Mode 1 except that the ADC
current will now be less than 9.5 mA.
Table VII. Receive Section Activation
RxON Pin
RxON Bit
Receive Section
0
OFF
01
ON
10
ON
11
ON
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