參數(shù)資料
型號： AD7731BR-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 19/44頁
文件大?。?/td> 0K
描述： IC ADC 24BIT SIGMA-DELTA 24-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 6.4k
數(shù)據(jù)接口： DSP，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 125mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
配用： EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731
AD7731
–26–
REV. 0
Chop Mode (SKIP = 0, CHP = 1)
With CHOP mode enabled and SKIP mode disabled, the sec-
ond stage filter is presented with alternating first stage filter
outputs and processes data accordingly. It has two primary
functions. One is to set the overall frequency response and the
second is to eliminate the modulated offset effect which appears
on the output of the first stage filter. Time to first output is
22
× 1/Output Rate in this mode. Table XVIII summarizes the
settling time and subsequent throughput rate for the various
different modes.
Figure 9 shows the full frequency response of the AD7731 when
the second stage filter is set for normal FIR operation. This
response is for chop mode enabled with the decimal equivalent
of the word in the SF bits set to 512 and a master clock fre-
quency of 4.9152 MHz. The response will scale proportionately
with master clock frequency. The response is shown from dc to
100 Hz. The rejection at 50 Hz
± 1 Hz and 60 Hz ± 1 Hz is
better than 88 dB.
The –3 dB frequency for the frequency response of the AD7731
with the second stage filter set for normal FIR operation and
chop mode enabled is determined by the following relationship:
f
3 dB = 0. 0395 × f MOD ×
1
3
× SF
CHP
= 1
()
In this case, f3dB = 7.9 Hz and the stop-band, where the attenua-
tion is greater than 64.5 dB, is determined by:
f
STOP = 0.14 × f MOD ×
1
3
× SF
CHP
= 1
()
In this case, fSTOP = 28 Hz.
FREQUENCY – Hz
0
–60
–100
090
GAIN
–
dB
10
20
30
40
50
60
70
80
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
100
Figure 9. Detailed Full Frequency Response of AD7731
(SKIP = 0, CHP = 1, SF = 512)
Figure 10 shows the frequency response for the same set of
conditions as for Figure 9 but in this case the response in shown
out to 600 Hz. This response shows that the attenuation of
input frequencies close to 200 Hz and 400 Hz is significantly
less than at other input frequencies. These “peaks” in the fre-
quency response are a by-product of the chopping of the input.
The plot of Figure 10 is the amplitude for different input fre-
quencies. Note that because the output rate is 200 Hz for the
conditions under which Figure 10 is plotted, if something ex-
isted in the input frequency domain at 200 Hz, it would be
aliased and appear in the output frequency domain at dc.
Because of this effect, care should be taken in choosing an out-
put rate which is close to the line frequency in the application.
For example, if the line frequency is 50 Hz, an output update
rate of 50 Hz should not be chosen as it will significantly reduce
the AD7731’s line frequency rejection (the 50 Hz will appear as
a dc component with only 6 dB attenuation). However, choos-
ing 60 Hz as the output rate (SF = 1707) will give better than
90 dB attenuation of the aliased line frequency. In a similar
fashion, if the line frequency is 60 Hz, it is recommended that
the user choose an output update rate of 50 Hz (SF = 2048).
FREQUENCY – Hz
0
–60
–100
0
450
GAIN
–
dB
50
100 150 200 250 300 350 400
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
500 550
600
Figure 10. Expanded Full Frequency Response of AD7731
(SKIP = 0, CHP = 1, SF = 512)
Similarly, multiples of the line frequency should be avoided as
the output rate because harmonics of the line frequency will not
be fully attenuated. The programmability of the AD7731’s
output rate should allow the user to readily choose an output
rate which overcomes this issue. An alternative is to use the part
in nonchop mode.
REV. A
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