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參數(shù)資料
| 型號(hào)： | AD7731BRU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.4k |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–30–
REV. 0
Internal Full-Scale Calibration
An internal full-scale calibration is initiated on the AD7731 by
writing the appropriate values (1, 0, 1) to the MD2, MD1 and
MD0 bits of the Mode Register. In this calibration mode, the
full-scale point used in determining the calibration coefficients is
with an internally-generated full-scale voltage. This full-scale
voltage is derived from the reference voltage for the AD7731
and the PGA is set for the selected gain (as per the RN2, RN1,
RN0 bits in the Mode Register) for this internal full-scale cali-
bration conversion.
Normally, the internal full-scale calibration is performed at the
required operating output range. When operating with a 20 mV
or 40 mV input range, it is recommended that internal full-scale
calibrations are performed on the 80 mV input range.
The internal full-scale calibration is a two-step sequence which
runs when an internal full-scale calibration command is written
to the AD7731. One part of the calibration is a zero-scale cali-
bration and as a result, the contents of the Offset Calibration
Register are altered during this Internal Full-Scale Calibration.
The user must, therefore, perform a zero-scale calibration
(either internal or system) AFTER the internal full-scale cali-
bration. This means that internal full-scale calibrations cannot
be performed in isolation.
The duration time of the calibration depends upon the CHP bit
of the Filter Register. With CHP = 1, the duration is 44
× 1/
Output Rate; with CHP = 0, the duration is 48
× 1/Output
Rate. At this time the MD2, MD1 and MD0 bits in the Mode
Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).
The
RDY line goes high when calibration is initiated and re-
turns low when calibration is complete. Note, the part has not
performed a conversion at this time. The user must write either
0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode
Register to initiate a conversion. If
RDY is low before (or goes
low during) the calibration command write to the Mode Regis-
ter, it may take up to one modulator cycle (MCLK IN/16) be-
fore
RDY goes high to indicate that calibration is in progress.
Therefore,
RDY should be ignored for up to one modulator
cycle after the last bit of the calibration command is written to
the Mode Register.
System Zero-Scale Calibration
System calibration allows the AD7731 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration but uses voltage values presented by the system to
the AIN inputs for the zero- and full-scale points.
A system zero-scale calibration is initiated on the AD7731 by
writing the appropriate values (1, 1, 0) to the MD2, MD1 and
MD0 bits of the Mode Register. In this calibration mode with a
unipolar input range, the zero-scale point used in determining
the calibration coefficients is the bottom end of the transfer
function. The system’s zero-scale point is applied to the AD7731’s
AIN input before the calibration step and this voltage must
remain stable for the duration of the system zero-scale calibra-
tion. The PGA is set for the selected gain (as per the RN2,
RN1, RN0 bits in the Mode Register) for this system zero-scale
calibration conversion. The allowable range for the system zero-
scale voltage is discussed in the Span and Offsets Section.
The duration time of the calibration depends upon the CHP bit
of the Filter Register. With CHP = 1, the duration is 22
× 1/
Output Rate; with CHP = 0, the duration is 24
× 1/Output
Rate. At this time the MD2, MD1 and MD0 bits in the Mode
Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).
The
RDY line goes high when calibration is initiated and re-
turns low when calibration is complete. Note, the part has not
performed a conversion at this time; it has simply performed a
zero-scale calibration and updated the Offset Calibration Regis-
ter for the selected channel. The user must write either 0, 0, 1
or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode Register to
initiate a conversion. If
RDY is low before (or goes low during)
the calibration command write to the Mode Register, it may
take up to one modulator cycle (MCLK IN/16) before
RDY
goes high to indicate that calibration is in progress. Therefore,
RDY should be ignored for up to one modulator cycle after the
last bit of the calibration command is written to the Mode Register.
For bipolar input ranges in the system zero-scale calibrating
mode, the sequence is very similar to that just outlined. In this
case, the zero-scale point is the mid-point of the AD7731’s
transfer function.
The system zero-scale calibration needs to be performed as one
part of a two part full calibration. However, once a full cali-
bration has been performed, additional system zero-scale
calibrations can be performed by themselves to adjust the
part’s zero-scale point only. When performing a two-step full
calibration, care should be taken as to the sequence in which the
two steps are performed. If the system zero-scale calibration is
one part of a full system calibration, it should take place before a
system full-scale calibration. If it takes place in association with
an internal full-scale calibration, this system zero-scale calibra-
tion should be performed after the full-scale calibration.
System Full-Scale Calibration
A system full-scale calibration is initiated on the AD7731 by
writing the appropriate values (1, 1, 1) to the MD2, MD1 and
MD0 bits of the Mode Register. System full-scale calibration is
performed using the system’s positive full-scale voltage. This
full-scale voltage must be set up before the calibration is initi-
ated, and it must remain stable throughout the calibration step.
The system full-scale calibration is performed at the selected
gain (as per the RN2, RN1, RN0 bits in the Mode Register).
The duration time of the calibration depends upon the CHP bit
of the Filter Register. With CHP = 1, the duration is 22
× 1/
Output Rate; with CHP = 0, the duration is 24
× 1/Output Rate.
At this time the MD2, MD1 and MD0 bits in the Mode Regis-
ter return to 0, 0, 0 (Sync or Idle Mode for the AD7731). The
RDY line goes high when calibration is initiated and returns low
when calibration is complete. Note, the part has not performed
a conversion at this time; it has simply performed a full-scale
calibration and updated the Gain Calibration Register for the
selected channel. The user must write either 0, 0, 1 or 0, 1, 0 to
the MD2, MD1, MD0 bits of the Mode Register to initiate a
conversion. If
RDY is low before (or goes low during) the cali-
bration command write to the Mode Register, it may take up to
one modulator cycle (MCLK IN/16) before
RDY goes high to
indicate that calibration is in progress. Therefore,
RDY should
be ignored for up to one modulator cycle after the last bit of the
calibration command is written to the Mode Register.
REV. A
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| AD7731BRUZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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| AD7731BRZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 5MSPS SOIC-24 |
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