參數(shù)資料
型號: AD7787BRMZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 1/20頁
文件大小: 0K
描述: IC ADC 24BIT 2CH LP SIG 10MSOP
標準包裝: 3,000
位數(shù): 24
采樣率(每秒): 120
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 225µW
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個單端,單極;1 個單端,雙極;1 個差分,單極;1 個差分,雙極
Low Power, 2-Channel
24-Bit Sigma-Delta ADC
Data Sheet
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2004–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Power
Supply: 2.5 V to 5.25 V operation
Normal mode: 75 A max
Power-down mode: 1 A max
RMS noise: 1.1 V at 9.5 Hz update rate
19.5-bit p-p resolution (22 bits effective resolution)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Rail-to-rail input buffer
VDD monitor channel
Temperature range: 40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI, QSPI, MICROWIRE, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
GENERAL DESCRIPTION
The AD7787 is a low power, complete analog front end for low
frequency measurement applications. It contains a low noise
24-bit Σ-Δ ADC with one differential input and one single-
ended input that can be buffered or unbuffered.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 V at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a
reduction in the current consumption. The update rate, cutoff
frequency, and settling time scales with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 W maximum. It is housed in a 10-lead MSOP.
FUNCTIONAL BLOCK DIAGRAM
04477-0-001
CLOCK
Σ-
ADC
AIN1(–)
AIN1(+)
GND
REFIN
AD7787
AIN2
VDD
BUF
DOUT/RDY
DIN
SCLK
CS
SERIAL
INTERFACE
AND
LOGIC
CONTROL
MUX
VDD
GND
Figure 1.
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