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參數(shù)資料
| 型號： | AD7790B |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | Low Power, 16-Bit Buffered Sigma-Delta ADC |
| 中文描述： | 低功耗，16位緩沖Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 299K |
| 代理商： | AD7790B |
AD7790
Bit Location
MR2
MR1
Rev. 0 | Page 12 of 20
Bit Name
0
BUF
Description
This bit must be programmed with a Logic 0 for correct operation.
Configures the ADC for buffered or unbuffered mode of operation. If
cleared
, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If
set
, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system.
This bit must be programmed with a Logic 0 for correct operation.
MR0
Table 10. Operating Modes
MD1
MD0
0
0
0
Mode
Continuous Conversion Mode
(Default)
Reserved
Single Conversion Mode
Power-Down Mode
0
1
1
1
0
1
Table 11. Analog Input Ranges
G1
0
0
1
1
G0
0
1
0
1
Range
±V
REF
±V
REF
/2
±V
REF
/4
±V
REF
/8
AD7790 LSB Size with V
REF
= +2.5 V
(μV)
76.3
38.14
19.07
9.54
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word
rate. Table 12 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the
filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
FR7
0(0)
Table 12. Filter Register Bit Designations
Bit Location
Bit Name
FR7–FR6
0
FR5–FR4
CLKDIV1–
CDIV0
FR3
0
FR2–FR0
FS2–FS0
FR6
0(0)
FR5
CDIV1(0)
FR4
CDIV0(0)
FR3
0(0)
FR2
FS2(1)
FR1
FS1(0)
FR0
FS0(0)
Description
These bits must be programmed with a Logic 0 for correct operation.
These bits are used to operate the AD7790 in the lower power modes. The clock is internally divided and
the power is reduced.
00
Normal Mode
01
Clock Divided by 2
10
Clock Divided by 4
11
Clock Divided by 8
This bit must be programmed with a Logic 0 for correct operation.
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and
noise. The noise is the same for all gain settings. See Table 13 for the allowable update rates in full power
mode. In the low power modes, the update rates will be reduced. (See Reduced Current Modes.)
Table 13. Update Rates
FS2
FS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FS0
0
1
0
1
0
1
0
1
f
ADC
(Hz)
120
100
33.3
20
16.6
16.7
13.3
9.5
f3dB (Hz)
28
24
8
4.7
4
4
3.2
2.3
RMS Noise (μV)
40
25
3.36
1.6
1.5
1.5
1.2
1.1
Rejection
25 dB @ 60 Hz
25 dB @ 50 Hz
80 dB @ 60 Hz
65 dB @ 50 Hz/60 Hz (Default Setting)
80 dB @ 50 Hz
62 dB @ 50/60 Hz
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
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