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參數(shù)資料
| 型號(hào)： | AD7790BRM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Power, 16-Bit Buffered Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MSOP-10 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 299K |
| 代理商： | AD7790BRM-REEL |
AD7790
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions,
set
implies a Logic 1 state and
cleared
implies a Logic 0 state, unless otherwise stated.
Rev. 0 | Page 10 of 20
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7
WEN(0)
Table 5. Communications Register Bit Designations
Bit Location
Bit Name
CR7
WEN
CR6
0(0)
CR5
RS1(0)
CR4
RS0(0)
CR3
R/W(0)
CR2
CREAD(0)
CR1
CH1(0)
CR0
CH0(0)
Description
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
This bit must be programmed to Logic 0 for correct operation.
Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 6.
A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
These bits are used to select the analog input channel. The differential channel can be selected
(AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to
digital conversion. Any change in channel resets the filter and a new conversion is started.
CR6
CR5–CR4
0
RS1–RS0
CR3
R/W
CR2
CREAD
CR1–CR0
CH1–CH0
Table 6. Register Selection
RS1
RS0
0
0
Register
Communications Register
during a Write Operation
Status Register during a
Read Operation
Mode Register
Filter Register
Data Register
Register Size
8-Bit
0
0
8-Bit
0
1
1
1
0
1
8-Bit
8-Bit
16-Bit
Table 7. Channel Selection
CH1
CH0
Channel
0
0
AIN(+) – AIN(–)
0
1
Reserved
1
0
AIN(–) – AIN(–)
1
1
V
DD
Monitor
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