參數(shù)資料
型號(hào): AD7793BRUZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/33頁(yè)
文件大小: 0K
描述: IC ADC 24BIT SIG-DEL 3CH 16TSSOP
設(shè)計(jì)資源: Fully Isolated Input Module Based on AD7793 and ADuM5401(CN0066)
Fully Isolated Input Module Based on AD7793, ADuM5401, and a High Performance In-Amp (CN0067)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 500
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸入數(shù)目和類型: 3 個(gè)差分,單極;3 個(gè)差分,雙極
產(chǎn)品目錄頁(yè)面: 779 (CN2011-ZH PDF)
配用: EVAL-AD7793EBZ-ND - BOARD EVALUATION FOR AD7793
AD7792/AD7793
Rev. B | Page 20 of 32
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7792/AD7793 are low power ADCs that incorporate a
∑-Δ modulator, a buffer, reference, in-amp, and an on-chip
digital filter intended for the measurement of wide dynamic
range, low frequency signals such as those in pressure
transducers, weigh scales, and temperature measurement
applications.
The part has three differential inputs that can be buffered or
unbuffered. The device can be operated with the internal 1.17 V
reference, or an external reference can be used. Figure 12 shows
the basic connections required to operate the part.
048
55-
012
DOUT/RDY
DIN
SCLK
CS
DVDD
SERIAL
INTERFACE
AND
CONTROL
LOGIC
Σ-Δ
ADC
AD7792/AD7793
AIN2(+)
REFIN(+)
REFIN(–)
AIN2(–)
AVDD
GND
MUX
BAND GAP
REFERENCE
INTERNAL
CLOCK
CLK
GND
AVDD
IN-AMP
BUF
REFIN(+) REFIN(–)
VBIAS
AIN1(+)
AIN1(–)
R
THERMOCOUPLE
JUNCTION
C
RREF
IOUT2
Figure 12. Basic Connection Diagram
The output rate of the AD7792/AD7793 (fADC) is user-program-
mable. The allowable update rates, along with their corresponding
settling times, are listed in Table 16. Normal mode rejection is
the major function of the digital filter. Simultaneous 50 Hz and
60 Hz rejection is optimized when the update rate equals
16.7 Hz or less as notches are placed at both 50 Hz and 60 Hz
with these update rates. See Figure 14.
The AD7792/AD7793 use slightly different filter types,
depending on the output update rate so that the rejection of
quantization noise and device noise is optimized. When the
update rate is from 4.17 Hz to 12.5 Hz, a Sinc3 filter, along with
an averaging filter, is used. When the update rate is from
16.7 Hz to 39 Hz, a modified Sinc3 filter is used. This filter
provides simultaneous 50 Hz/60 Hz rejection when the update
rate equals 16.7 Hz. A Sinc4 filter is used when the update rate
is from 50 Hz to 242 Hz. Finally, an integrate-only filter is used
when the update rate equals 470 Hz.
Figure 13 to Figure 16 show the frequency response of the
different filter types for several update rates.
0
–20
–40
–60
–80
–100
0
120
100
80
60
40
20
04
85
5-
01
8
FREQUENCY (Hz)
(dB
)
Figure 13. Filter Profile with Update Rate = 4.17 Hz
0
–20
–40
–60
–80
–100
0
200
180
160
140
120
100
80
60
40
20
04
85
5-
0
19
FREQUENCY (Hz)
(d
B
)
Figure 14. Filter Profile with Update Rate = 16.7 Hz
0
–20
–40
–60
–80
–100
0
3000
2500
2000
1500
1000
500
04
85
5-
0
20
FREQUENCY (Hz)
(d
B
)
Figure 15. Filter Profile with Update Rate = 242 Hz
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