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參數(shù)資料
| 型號(hào)： | AD7801BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | AD7801BR |
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AD7801
–7–
REV. 0
T E RMINOLOGY
Integral Nonlinearity
For the DAC, Relative Accuracy or End-Point nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A graphical representation of the transfer curve is
shown in Figure 14.
Differential Nonlinearity
Differential Nonlinearity is the difference between the mea-
sured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of
±
1 LSB
maximum ensures monotonicity.
Zero-Code E rror
Zero-Code Error is the measured output voltage from V
OUT
of
the DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in LSBs.
Gain E rror
T his is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. It includes full-
scale errors but not offset errors.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into
the analog output when the digital inputs change state with
the DAC selected and the
LDAC
used to update the DAC. It
is normally specified as the area of the glitch in nV-secs and
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Rejection Ratio (PSRR)
T his specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power supply rejection
ratio is quoted in terms of % change in output per % change in
V
DD
for full-scale output of the DAC. V
DD
is varied
±
10%.
GE NE RAL DE SCRIPT ION
D/A Section
T he AD7801 is an 8-bit voltage output digital-to-analog con-
verter. T he architecture consists of a reference amplifier and a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
AD7801
V
OUT
REFIN
I/V
11.7k
11.7k
CURRENT
DAC
30k
30k
V
DD
REFERENCE
AMPLIFIER
Figure 19. DAC Architecture
T he DAC output is internally buffered and has rail-to-rail
output characteristics. T he output amplifier is capable of driving
a load of 100 pF and 10 k
to both V
DD
and ground. T he
reference selection for the DAC can be either internally gener-
ated from V
DD
or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
V
DD
, the reference selected is the internally generated V
DD
/2
reference. When an externally applied voltage is more than one
volt below V
DD
, the comparator selection switches to the externally
applied voltage on the REFIN pin. T he range on the external
reference input is from 1.0 V to V
DD
/2 V. T he output voltage
from the DAC is given by:
V
O
=
2
V
REF
×
N
256
where
V
REF
is the voltage applied to the external REFIN pin or
V
DD
/2 when the internal reference is selected.
N
is the decimal
equivalent of the code loaded to the DAC register and ranges
from 0 to 255.
VTH
PMOS
MUX
INT
REF
COMPARATOR
SELECTED REFERENCE
OUTPUT
V
DD
REF
IN
INT REF
EXT REF
Figure 20. Reference Selection Circuitry
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