參數(shù)資料
型號(hào)： AD7801BRU
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC
中文描述： PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO20
封裝： TSSOP-20
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 219K
代理商： AD7801BRU
AD7801
–9–
REV. 0
V
OUT
=
2
×
V
REF
N
256
where:
N
is the decimal equivalent of the binary input
code. N ranges from 0 to 255.
V
REF
is the voltage applied to the external REFIN pin
when the external reference is selected and is V
DD
/2
if the internal reference is used.
T able I. Output Voltage for Selected Input Codes
Digital
MSB . . . LSB
Analog Output
1111 1111
2
×
254
256
×
V
REF
V
2
×
255
256
×
V
REF
V
1111 1110
2
×
129
256
×
V
REF
V
V
REF
V
2
×
127
256
×
V
REF
V
1000 0001
1000 0000
0111 1111
0000 0001
0
V
2
×
V
REF
256
V
0000 0000
2V
REF
V
REF
0
D
DAC INPUT CODE
00 01
7F 80 81
FE FF
Figure 26. DAC Transfer Function
POWE R-ON RE SE T
T he AD7801 has a power-on reset circuit designed to allow
output stability during power up. T his circuit holds the DAC in
a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input register of the DAC and
the DAC register is in transparent mode thus the output of the
DAC is held at ground potential until a write takes place to the
DAC. T he power-on reset circuitry generates a PON ST RB
signal which is a gating signal used within the logic to identify
a power-on condition.
POWE R-DOWN FE AT URE S
T he AD7801 has a power-down feature implemented by
exercising the external
PD
pin. An active low signal puts the
complete DAC into power-down mode. When in power-down,
the current consumption of the device is reduced to less than
1
μ
A max at +25
°
C or 2
μ
A max over temperature, making the
device suitable for use in portable battery powered equipment.
T he internal reference resistors, the reference bias servo loop,
the output amplifier and associated linear circuitry are all shut
down when the power-down is activated. T he output terminal
sees a load of
≈
23 k
to GND when in power-down mode as
shown in Figure 25. T he contents of the data register are
unaffected when in power-down mode. T he device typically
comes out of power-down in 13
μ
s (see Figure 10).
V
DD
11.7k
11.7k
I
DAC
V
REF
Figure 25. Output Stage During Power-Down
Analog Outputs
T he AD7801 contains a voltage output DAC with 8-bit resolution
and rail-to-rail operation. T he output buffer provides a gain of
two at the output. Figures 2, 3 and 4 show the source and sink
capabilities of the output amplifier. T he slew rate of the output
amplifier is typically 7.5 V/
μ
s and has a full-scale settling to
eight bits with a 100 pF capacitive load in typically 1.2
μ
s.
T he input coding to the DAC is straight binary. T able I shows
the binary transfer function for the AD7801. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
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