參數(shù)資料
型號： AD7801BRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 3/16頁
文件大小： 0K
描述： IC DAC 8BIT PARALLEL INP 20TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 75
設(shè)置時間： 1.2µs
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 12.9mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 833k
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD7801
–11–
REV. 0
In the circuit shown the
LDAC is hardwired low thus the DAC
output is updated on the rising edge of
WR. Some applications
may require synchronous updating of the DAC in the AD7801.
In this case the
LDAC signal can be driven from an external
timer or can be controlled by the microprocessor. One option
for synchronous updating is to decode the
LDAC from the ad-
dress bus so a write operation at this address will synchronously
update the DAC output. A simple OR gate with one input
driven from the decoded address and the second input from the
WR signal will implement this function.
AD7801–8051/8088 Interface
Figure 31 shows a serial interface between the AD7801 and the
8051/8088 processors.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
A15
A8
PSEN OR DEN
WR
AD7
AD0
8051/8088*
ALE
OCTAL
LATCH
Figure 31. AD7801–8051/8088 Interface
APPLICATIONS
Bipolar Operation Using the AD7801
The AD7801 has been designed for unipolar operation but
bipolar operation is possible using the circuit in Figure 32. The
circuit shown is configured for an output voltage range of –5 V
to +5 V. Rail-to-rail operation at the amplifier output is achievable
by using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
VO = R2 1+
R4
R3
/ R1
+ R2
()× 2VREFD
256
V
REF
R4
R3
Where D is the decimal equivalent of the code loaded to the
DAC and VREF is the reference voltage input.
With VREF = 2.5 V, R1 = R3 = 10 k
and R2 = R4 = 20 k and
VDD = 5 V.
VO =
10D
256
–5
DATA
BUS
CONTROL
INPUTS
AD7801
CS WR LDAC
VOUT
D7-D0
CLR
PD
VDD
REF IN
VDD = 3V TO 5V
VDD AGND DGND
10 F
0.1 F
EXT REF V
OUT
VIN
GND
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
R1
10k
R2
20k
+5V
±5V
R3
10k
R4
20k
–5V
AD820/
OP295
Figure 32. Bipolar Operation Using the AD7801
Decoding Multiple AD7801s in a System
The
CS pin on the AD7801 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same input data, but only the
CS to one of
the DACs will be active at any one time allowing access to one
channel in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the Enable input on the
74HC139 should be brought to its inactive state while the
Coded Address inputs are changing state. Figure 33 shows a
diagram of a typical setup for decoding multiple AD7801
devices in a system. The built-in power-on reset circuit on the
AD7801 ensures that the outputs of all DACs in the system
power up with zero volts on their outputs.
AD7801
CS
WR
D0
D7
LDAC
VOUT
AD7801
CS
WR
D0
D7
LDAC
VOUT
AD7801
CS
WR
D0
D7
LDAC
VOUT
AD7801
CS
WR
D0
D7
LDAC
VOUT
74HC139
VCC
VDD
1
G
1A
1B
DGND
ENABLE
CODED
ADDRESS
WR
1Y0
1Y1
1Y2
1Y3
DATA BUS
Figure 33. Decoding Multiple AD7801s
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