VBIAS 2 32 MAIN DAC RANGE SUB DAC RANGE CHANNEL RANGE MIN CODE L" />
參數(shù)資料
型號(hào)： AD7804BR
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT 3.3V QUAD 16-SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 47
設(shè)置時(shí)間： 1.5µs
位數(shù)： 10
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 66mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
輸出數(shù)目和類(lèi)型： 8 電壓，雙極
采樣率（每秒）： 667k
AD7804/AD7805/AD7808/AD7809
REV. A
–20–
VBIAS
2
32
MAIN DAC RANGE
SUB DAC
RANGE
CHANNEL RANGE MIN CODE LOADED TO SUB DAC
CHANNEL RANGE CENTER CODE LOADED TO SUB DAC
CHANNEL RANGE MAX CODE LOADED TO SUB DAC
VBIAS
32
VBIAS
62
32
VBIAS
1
32
VBIAS
3
32
VBIAS
31
32
VBIAS
33
32
VBIAS
61
32
VBIAS
63
32
Figure 28. Pictorial View of Transfer Function for Any DAC Channel
Grounding and Layout Techniques
To obtain optimum performance from the AD7804/AD7805/
AD7808/AD7809 care should be taken with the layout. Causes
for concern would be feedthrough from the interface bus onto
the analog circuitry particularly the reference pins and ground
loops. The board should be designed such that the analog and
digital sections are separated as much as possible. Ground plan-
ing and shielding should be used as much as possible. Digital
and analog ground planes should only be joined in one place to
avoid ground loops. The ideal place to join the ground planes is
at the analog and digital ground pins of the DAC. Alternatively
a star ground should be established on the board to which all
other grounds are returned. Good decoupling is important in
achieving optimum performance. All supplies, analog or digital,
should be decoupled with 10
F tantalum and 0.1 F ceramic
capacitors to their respective grounds, and should be as close as
possible to the pins of the device. The main aim of the bypass-
ing element is to maximize the charge stored in the bypass loop
while simultaneously minimizing the inductance of this loop.
Inductance in the loop acts as an impedance to high frequency
transients and results in power supply spiking. By keeping the
decoupling as close as possible to the device, the loop area is kept
to a minimum thus reducing the possibility of power supply spikes.
On the AD7805 the REFOUT pin of the device is located next
to the DB9 of the data bus, to reduce the risk of digital feed-
through and noise being coupled from the digital section onto
the reference, the REFOUT pin and any trace connected to it
should be shielded with analog ground. To reduce the noise on
this reference it should be decoupled with a 0.01
F capacitor to
analog ground, keeping the capacitor as close as possible to the
device. The comp pin which is the output from the internal
VDD/2 reference is located next to VOUTD on the DAC and is
sensitive to noise pickup and feedthrough from the DAC output
and thus should be shielded with analog ground to keep this
reference point as quiet as possible. The comp pin should be
decoupled both to AVDD and AGND with 1–10 nF ceramic
capacitors. The external REFIN pin should also be shielded
with analog ground from the digital pins located next to it.
The same precautions should be taken with the reference pins
on the AD7804/AD7808 to reduce the risk of noise pickup and
feedthrough.
Reference Settling Time
With the REFOUT on the AD7804/AD7805/AD7808/AD7809
decoupled with a 0.01
F capacitor to AGND it takes the
REFOUT approximately 2 ms to fully settle after taking the
device out of power down. When this capacitor is reduced to
1 nF the settling time reduces to 150
s. The size of the capaci-
tor required on the REFOUT depends to a large extent on the
layout, if the REFOUT is well shielded with AGND the size of
the capacitor can be reduced thus reducing the settling time for
the reference. The internal VDD/2 reference provided at the
comp pin when decoupled with a 1 nF capacitor to both AVDD
and AGND has very fast settling time, typically less than 500 ns.
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