AD7805/AD7809 TIMING CHARACTERISTICS1 (V " />
參數(shù)資料
型號(hào): AD7805CR
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD PARALL 28-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 27
設(shè)置時(shí)間: 1.5µs
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字
功率耗散(最大): 66mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
輸出數(shù)目和類型: 8 電壓,雙極
采樣率(每秒): 667k
AD7804/AD7805/AD7808/AD7809
–5–
REV. A
AD7805/AD7809 TIMING CHARACTERISTICS1 (V
DD = 3.3 V
10% to 5 V
10%; AGND = DGND = 0 V; Reference
= Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
Limit at TMIN, TMAX
Parameter
All Versions
Unit
Description
t1
25
ns min
Mode Valid to Write Setup Time
t2
4.5
ns min
Mode Valid to Write Hold Time
t3
25
ns min
Address Valid to Write Setup Time
t4
4.5
ns min
Address Valid to Write Hold Time
t5
25
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t6A
6
ns min
LDAC Valid to Write Hold Time
t7
40
ns min
Chip Select to Write Setup Time
t8
0
ns min
Chip Select to Write Hold Time
t9
40
ns min
Write Pulsewidth
t10
100
ns min
Time Between Successive Writes
t11
40
ns min
LDAC, CLR Pulsewidth
t12
100
ns min
Write to
LDAC Setup Time
NOTE
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.
Specifications subject to change without notice.
MODE
CS
WR
DATA
LDAC 2
CLR
LDAC 1
t
1
t
2
t
3
t
4
t
7
t
8
t
9
t
5
t
6
t
10
t
11
t
12
t
11
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
t
6A
A0, A1, A2
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
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