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參數(shù)資料
| 型號： | AD7811YRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 4CHAN SRL 16-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 350k |
| 數(shù)據(jù)接口： | DSP，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；3 個偽差分，單極 |
AD7811/AD7812
–12–
REV. B
When using automatic power-down between conversions to
improve the power performance of the part (see Power vs.
Throughput) the switch SW1 will open when the part enters its
power-down mode if using the internal on-chip reference. This
provides a high impedance discharge path for the external
capacitor (see Figure 9). A typical value of external capacitance
is 10 nF. When the part is in Mode 2 Full Power-Down, because
the external capacitor holds its charge during power-down, the
internal bandgap reference will power up more quickly after
relatively short periods of full power-down. When operating the
part in Mode 2 Partial Power-Down the external capacitor is not
required as the on-chip reference stays powered up while the
rest of the circuitry powers down.
ADC TRANSFER FUNCTION
The output coding of the AD7811 and AD7812 is straight
binary. The designed code transitions occur at successive inte-
ger LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is =
VREF/1024. The ideal transfer characteristic for the AD7811 and
AD7812 is shown in Figure 10.
000...000
0V
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
1LSB
+VREF–1LSB
1LSB = VREF /1024
ADC
CODE
Figure 10. AD7811 and AD7812 Transfer Characteristic
POWER-DOWN OPTIONS
The AD7811 and AD7812 provide flexible power management
to allow the user to achieve the best power performance for a
given throughput rate.
The power management options are selected by programming
the power-down bits (i.e., PD1 and PD0) in the control register.
Table III below summarizes the options available. When the
power-down bits are programmed for Mode 2 Power Down (full
and partial), a rising edge on the
CONVST pin will power up
the part. This feature is used when powering down between
conversions—see Power vs. Throughput. When the AD7811
and AD7812 are placed in partial power-down the on-chip
reference does not power down. However, the part will power
up more quickly after long periods of power-down when using
partial power-down—see Power-Up Times section.
Table III. AD7811/AD7812 Power-Down Options
PD1
PD0
CONVST*
Description
1
x
Full Power-Up
0
x
Full Power-Down
0
1
0
Mode 2 Partial Power-Down
(Reference Stays Powered-Up)
0
1
No Power-Down
1
0
Mode 2 Full Power-Down
1
0
1
No Power-Down
*This refers to the state of the CONVST signal at the end of a conversion.
POWER-ON-RESET
If during normal operation, a power-save is performed by removing
power from the AD7811 and AD7812; the user must be wary
that a proper reset is done when power is applied to the part
again. To ensure proper power-on-reset, we recommend that
both PD bits are set to 0 and then set to 1. This procedure
causes an internal reset to occur.
POWER-UP TIMES
The AD7811 and AD7812 have a 1.5
s power-up time when
using an external reference or when powering up from partial
power-down. When VDD is first connected, the AD7811 and
AD7812 are in a low current mode of operation. In order to
carry out a conversion the AD7811 and AD7812 must first be
powered up by writing to the control register of each ADC to
set the power-down bits (i.e., PD1 = 1, PD0 = 1) for a full
power-up. See the Quick Evaluation Setup section on the fol-
lowing page.
Mode 2 Full Power-Down (PD1 = 1, PD0 = 0)
The power-up time of the AD7811 and AD7812 after power is
first connected, or after a long period of Full Power-Down, is
the time it takes the on-chip 1.23 V reference to power up plus
the time it takes to charge the external capacitor CREF—see
Figure 9. The time taken to charge CREF to the 10-bit level is
given by the equation (7.6
× 2 k × CREF). For CREF = 10 nF
the power-up time is approximately 152
s. It takes 30 s to
power up the on-chip reference so the total power-up time of
either ADC in either of these conditions is 182
s. However,
when powering down fully between conversions to achieve a
better power performance this power-up time reduces to 1.5
s
after a relatively short period of power-down as CREF holds its
charge (see On-Chip Reference section). The AD7811 and
AD7812 can therefore be used in Mode 2 with throughput
rates of 250 kSPS and under.
Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1)
The power-up time of the AD7811 and AD7812 from a Partial
Power-Down is 1.5
s maximum. When using a Partial Power-
Down between conversions, there is no requirement to connect
an external capacitor to the C
REF pin because the reference
remains powered up. This means that the AD7811 and AD7812
will power up in 30
s after the supplies are first connected as
there is no requirement to charge an external capacitor.
POWER VS. THROUGHPUT
By using the Automatic Power-Down (Mode 2) at the end of a
conversion—see Operating Modes section of the data sheet,
superior power performance can be achieved.
Figure 11 shows how the Automatic Power-Down is implemented
using the
CONVST signal to achieve the optimum power
performance for the AD7811 and AD7812. The AD7811 and
AD7812 are operated in Mode 2 and the control register Bits
PD1 and PD0 are set to 1 and 0 respectively for Full Power-Down,
or 0 and 1 for Partial Power-Down. The duration of the
CONVST
pulse is set to be equal to or less than the power-up time of the
devices—see Operating Modes section. As the throughput rate
is reduced, the device remains in its power-down state longer
and the average power consumption over time drops accordingly.
C
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