VDD 6040 HEX NOT VALID 4040 HEX VALID DATA 4040 HEX t POWER-U" />
參數(shù)資料
型號(hào)： AD7811YRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/24頁(yè)
文件大小： 0K
描述： IC ADC 10BIT QUAD SRL 16-TSSOP
標(biāo)準(zhǔn)包裝： 96
位數(shù)： 10
采樣率（每秒）： 350k
數(shù)據(jù)接口： DSP，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；3 個(gè)偽差分，單極
AD7811/AD7812
–14–
REV. B
DIN
DOUT
CONVST
VDD
6040 HEX
NOT VALID
4040 HEX
VALID DATA
4040 HEX
t
POWER-UP
1.5 s
t
CONVERT
2.3 s
t
CONVERT
2.3 s
Figure 15. Read/Write Sequence for AD7812
OPERATING MODES
The mode of operation of the AD7811 and AD7812 is selected
when the (logic) state of the
CONVST is checked at the end of
a conversion. If the
CONVST signal is logic high at the end
of a conversion, the part does not power down and is operat-
ing in Mode 1. If, however, the
CONVST signal is brought
logic low before the end of a conversion, the AD7811 and AD7812
will power down at the end of the conversion. This is Mode 2
operation.
Mode 1 Operation (High Speed Sampling)
When the AD7811 and AD7812 are operated in Mode 1 they
are not powered down between conversions. This mode of opera-
tion allows high throughput rates to be achieved. The timing
diagram in Figure 16 shows how this optimum throughput rate
is achieved by bringing the
CONVST signal high before the end
of the conversion.
The sampling circuitry leaves its tracking mode and goes into
hold on the falling edge of
CONVST. A conversion is also initi-
ated at this time. The conversion takes 2.3
s to complete. At
this point, the result of the current conversion is latched into the
serial shift register and the state of the
CONVST signal checked.
The
CONVST signal should be logic high at the end of the
conversion to prevent the part from powering down. The serial
port on the AD7811 and AD7812 is enabled on the rising edge
of the first SCLK after the rising edge of the RFS signal—see
Serial Interface section. As explained earlier, this rising edge
should occur before the end of the conversion process if the part
is not to be powered down. A serial read can take place at any
stage after the rising edge of
CONVST. If a serial read is initi-
ated before the end of the current conversion process (i.e., at
time “A”), the result of the previous conversion is shifted out on
the DOUT pin. It is possible to allow the serial read to extend
beyond the end of a conversion. In this case the new data will
not be latched into the output shift register until the read
has finished. The dynamic performance of the AD7811 and
AD7812 typically degrades by up to 3 dBs while reading during
a conversion. If the user waits until the end of the conversion
process, i.e., 2.3
s after the falling edge of CONVST (Point
“B”) before initiating a read, the current conversion result is
shifted out. The serial read must finish at least 100 ns prior to
the next falling edge of
CONVST to allow the part to accurately
acquire the input signal.
Mode 2 Operation (Automatic Power-Down)
When used in this mode of operation the part automatically
powers down at the end of a conversion. This is achieved by
leaving the
CONVST signal low until the end of the conversion.
Because it takes approximately 1.5
s for the part to power-up
after it has been powered down, this mode of operation is intended
to be used in applications where slower throughput rates are
required, i.e., in the order of 250 kSPS and improved power
performance is required—see Power vs. Throughput section.
There are two power-down modes the AD7811/AD7812 can
CURRENT CONVERSION
RESULT
A
B
t
12
CONVST
DOUT
SCLK
t
1
t2
Figure 16. Mode 1 Operation Timing Diagram
C
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