參數(shù)資料
型號(hào)： AD7812YRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/24頁(yè)
文件大小： 0K
描述： IC ADC 10BIT 8-CHAN SRL 20-TSSOP
標(biāo)準(zhǔn)包裝： 75
位數(shù)： 10
采樣率（每秒）： 350k
數(shù)據(jù)接口： DSP，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；7 偽差分，單極
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
AD7811/AD7812
–15–
REV. B
enter during automatic power-down. These modes are discussed
in the Power-Up Times section of this data sheet. The timing
diagram in Figure 17 shows how to operate the part in Mode 2.
If the AD7811/AD7812 is powered down, the rising edge of the
CONVST pulse causes the part to power-up. Once the part
has powered up (~1.5
s after the rising edge of CONVST)
the
CONVST signal is brought low and a conversion is initiated
on this falling edge of the
CONVST signal. The conversion
takes 2.3
s and after this time the conversion result is latched
into the serial shift register and the part powers down. There-
fore, when the part is operated in Mode 2 the effective conver-
sion time is equal to the power-up time (1.5
s) and the SAR
conversion time (2.3
s).
NOTE: Although the AD7811 and AD7812 take 1.5
s to
power up after the rising edge of
CONVST, it is not necessary
to leave
CONVST high for 1.5
s after the rising edge before
bringing it low to initiate a conversion. If the
CONVST signal
goes low before 1.5
s in time has elapsed, then the power-up
time is timed out internally and a conversion is then initiated.
Hence the AD7811 and AD7812 are guaranteed to have always
powered-up before a conversion is initiated, even if the
CONVST
pulsewidth is <1.5
s. If the CONVST pulsewidth is > 1.5 s,
then a conversion is initiated on the falling edge.
As in the case of Mode 1 operation, the rising edge of the first
SCLK after the rising edge of RFS enables the serial port of the
AD7811 and AD7812 (see Serial Interface section). If a serial
read is initiated soon after this rising edge (Point “A”), i.e.,
before the end of the conversion, the result of the previous con-
version is shifted out on pin DOUT. In order to read the result
of the current conversion, the user must wait at least 2.3
s after
power-up or at least 2.3
s after the falling edge of CONVST,
(Point “B”), whichever occurs latest before initiating a serial
read. The serial port of the AD7811 and AD7812 is still func-
tional even though the devices have been powered down.
Because it is possible to do a serial read from the part while it is
powered down, the AD7811 and AD7812 are powered up only
to do the conversion and are immediately powered down at the
end of a conversion. This significantly improves the power
consumption of the part at slower throughput rates—see Power
vs. Throughput section.
SERIAL INTERFACE
The serial interface of the AD7811 and AD7812 consists of five
wires, a serial clock input, SCLK, receive data to clock syn-
chronization input RFS, transmit data to clock synchronization
input TFS, a serial data output, DOUT, and a serial data
input, DIN, (see Figure 18). The serial interface is designed to
allow easy interfacing to most microcontrollers and DSPs,
e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320
and ADSP-21xx, without the need for any gluing logic. When
interfacing to the 8051, the SCLK must be inverted. The
Microprocessor/Microcontroller Interface section explains
how to interface to some popular DSPs and microcontrollers.
Figure 18 shows the timing diagram for a serial read and write
to the AD7811 and AD7812. The serial interface works with
both a continuous and a noncontinuous serial clock. The rising
edge of RFS and falling edge of TFS resets a counter that
counts the number of serial clocks to ensure the correct number
of bits are shifted in and out of the serial shift registers. Once
the correct number of bits have been shifted in and out, the
SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the active edges of TFS and
CURRENT CONVERSION
RESULT
A
B
t
POWER-UP
CONVST
DOUT
SCLK
1.5 s
t
1
t
2
Figure 17. Mode 2 Operation Timing Diagram
A
B
DIN
DB9
DB8
DB9
DB7
DB8
DB7
DB6
DB5
DB4
DB3
DB0
SCLK
RFS
DOUT
t
3
t
7
t
4
t
10
DB1
DB2
1
13
12
11
10
9
8
7
6
5
4
3
2
TFS
t
8
t
9
t
5
t
6
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Figure 18. Serial Interface Timing Diagram
C
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