參數(shù)資料
型號: AD7813YRZ
廠商: Analog Devices Inc
文件頁數(shù): 11/11頁
文件大?。?/td> 0K
描述: IC ADC 10BIT PARALLEL 16-SOIC
標準包裝: 48
位數(shù): 10
采樣率(每秒): 400k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 17.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極
產(chǎn)品目錄頁面: 779 (CN2011-ZH PDF)
AD7813
–9–
REV. C
PARALLEL INTERFACE
The parallel interface of the AD7813 is eight bits wide. The
output data buffers are activated when both CS and RD are
logic low. At this point the contents of the data register are
placed on the 8-bit data bus. Figure 15 shows the timing dia-
gram for the parallel port. As previously explained, two succes-
sive read operations must take place in order to access the 10-bit
conversion result. The first read places the 8 MSBs on the data
bus and the second read places the 2 LSBs on the data bus. The
2 LSBs appear on DB7 and DB6, with DB5–DB0 set to logic zero.
Further read operations will access the 8 MSBs and 2 LSBs of
the 10-bit ADC conversion result again. The parallel interface
of the AD7813 is reset when BUSY goes logic high. This feature
allows the AD7813 to be used as an 8-bit converter if the user
only wishes to access the 8 MSBs of the conversion. Care must
be taken to ensure that a read operation does not occur while
BUSY is high. Data read from the AD7813 while BUSY is high
will be invalid. For optimum performance the read operation
should end at least 100 ns (t10) prior to the falling edge of the
next CONVST.
8 MSBs
t1
t2
t3
t POWER-UP
EXT
CONVST
INT
CONVST
BUSY
CS/RD
DB7–DB0
2 LSBs
Figure 13. Mode 1 Operation
8 MSBs
t1
t3
EXT
CONVST
INT
CONVST
BUSY
CS/RD
DB7–DB0
t POWER-UP
Figure 14. Mode 2 Operation
CONVST
BUSY
CS
DB7–DB0
t2
t3
t1
t4
t6
t7
t5
RD
t8
t9
8 MSBs
2 MSBs
Figure 15. Parallel Port Timing
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