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參數(shù)資料
| 型號： | AD7818AR-REEL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 3/5V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC; Package: SOIC; No of Pins: 8; Temperature Range: Commercial |
| 中文描述： | 與單核和4通道，9我們，10位ADC片上溫度傳感器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 279K |
| 代理商： | AD7818AR-REEL |
REV. C
AD7816/AD7817/AD7818
–5–
TIMING CHARACTERISTICS
1, 2
Parameter
A, B Versions
Unit
μ
s max
μ
s max
μ
s max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
Test Conditions/Comments
t
POWER-UP
t
1a
t
1b
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
123
t
133
t
14a3, 4
t
14b3, 4
t
15
t
16
t
17
2
9
27
20
50
0
0
10
10
40
40
0
0
20
20
30
30
150
40
400
Power-Up Time from Rising Edge of
CONVST
Conversion Time Channels 1 to 4
Conversion Time Temperature Sensor
CONVST
Pulse Width
CONVST
Falling Edge to BUSY Rising Edge
CS
Falling Edge to RD/
WR
Falling Edge Setup Time
RD/
WR
Falling Edge to SCLK Falling Edge Setup
D
IN
Setup Time before SCLK Rising Edge
D
IN
Hold Time after SCLK Rising Edge
SCLK Low Pulse Width
SCLK High Pulse Width
CS
Falling Edge to RD/
WR
Rising Edge Setup Time
RD/
WR
Rising Edge to SCLK Falling Edge Setup Time
D
OUT
Access Time after RD/
WR
Rising Edge
D
OUT
Access Time after SCLK Falling Edge
D
OUT
Bus Relinquish Time after Falling Edge of RD/
WR
D
OUT
Bus Relinquish Time after Rising Edge of
CS
BUSY
Falling Edge to
OTI
Falling Edge
RD/
WR
Rising Edge to
OTI
Rising Edge
SCLK Rising Edge to
CONVST
Falling Edge (Acquisition Time of T/H)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 16, 17, 20 and 21.
3
These figures are measured with the load circuit of Figure 3. They are defined as the time required for D
OUT
to cross 0.8 V or 2.4 V for V
DD
= 5 V 10% and 0.4 V
or 2 V for V
= 3 V 10%, as quoted on the specifications page of this data sheet.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6V
I
OL
200 A
200 A
I
OL
TO
OUTPUT
PIN
C
L
50pF
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
(V
DD
= 2.7 V to 5.5 V, GND = 0 V, REF
IN
= 2.5 V. All specifications T
MIN
to T
MAX
unless
otherwise noted)
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