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| 型號(hào)： | AD7819YRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SAMPLING PAR 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
REV. B
AD7819
–7–
During the acquisition phase the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (TCHARGE) is given by the fol-
lowing formula:
TCHARGE = 6.2
× (R2 + 125 ) × 3.5 pF
For small values of source impedance, the settling time associ-
ated with the sampling circuit (100 ns) is, in effect, the acquisition
time of the ADC. For example, with a source impedance (R2)
of 10
, the charge time for the sampling capacitor is approxi-
mately 3 ns. The charge time becomes significant for source
impedances of 2 k
and greater.
AC Acquisition Time
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of the
ADC. Large values of source impedance will cause the THD to
degrade at high throughput rates.
ADC TRANSFER FUNCTION
The output coding of the AD7819 is straight binary. The designed
code transitions occur at successive integer LSB values (i.e.,
1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal
transfer characteristic for the AD7819 is shown in Figure 7 below.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
ADC
CODE
1LSB = VREF/256
0V 1LSB
+VREF –1LSB
ANALOG INPUT
Figure 7. Transfer Characteristic
POWER-UP TIMES
The AD7819 has a 1.5
s power-up time. When VDD is first con-
nected, the AD7819 is in a low current mode of operation. In
order to carry out a conversion the AD7819 must first be pow-
ered up. The ADC is powered up by a rising edge on an internally
generated
CONVST signal, which occurs as a result of a rising
edge on the external
CONVST pin. The rising edge of the external
CONVST signal initiates a 1.5
s pulse on the internal CONVST
signal. This pulse is present to ensure the part has enough time
to power-up before a conversion is initiated, as a conversion is
initiated on the falling edge of gated
CONVST. See Timing and
Control section. Care must be taken to ensure that the
CONVST
pin of the AD7819 is logic low when VDD is first applied.
When operating in Mode 2, the ADC is powered down at the
end of each conversion and powered up again before the next
conversion is initiated. (See Figure 8.)
t POWER-UP
1.5 s
tPOWER-UP
1.5 s
tPOWER-UP
1.5 s
MODE 1
MODE 2
V
EXT
CONVST
INT
CONVST
VDD
EXT
CONVST
INT
CONVST
Figure 8. Power-Up Times
POWER VS. THROUGHPUT RATE
By operating the AD7819 in Mode 2, the average power con-
sumption of the AD7819 decreases at lower throughput rates.
Figure 9 shows how the Automatic Power-Down is implemented
using the external
CONVST signal to achieve the optimum
power performance for the AD7819. The AD7819 is operated
in Mode 2 and the duration of the external
CONVST pulse is
set to be equal to or less than the power-up time of the device.
As the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
EXT
CONVST
INT
CONVST
POWER-DOWN
tPOWER-UP
1.5 s
tCONVERT
4.5 s
tCYCLE
100 s @ 10kSPS
Figure 9. Automatic Power-Down
If, for example, the AD7819 is operated in a continuous sam-
pling mode with a throughput rate of 10 kSPS, the power
consumption is calculated as follows. The power dissipation
during normal operation is 10.5 mW, VDD = 3 V. If the power-
up time is 1.5
s and the conversion time is 4.5 s, the AD7819
can be said to dissipate 10.5 mW for 6
s (worst case) during
each conversion cycle. If the throughput rate is 10 kSPS, the
cycle time is then 100
s and the average power dissipated dur-
ing each cycle is (6/100)
× (10.5 mW) = 630 W.
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