參數(shù)資料
型號(hào)： AD7822BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20
封裝： MO-153AC, TSSOP-20
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 215K
代理商： AD7822BRU
AD7822/AD7825/AD7829
–10–
REV. A
CONVST
DB0-DB7
A0-A2
EOC
CS
RD
t
2
t
1
t
3
t
13
DATA
ADDRESS CHANNEL y
TRACK CHx
TRACK CHx
HOLD CHx
TRACK CHy
HOLD CHy
120ns
Figure 12. Channel Hopping Timing
There is a minimum time delay between the falling edge of
RD
and the next falling edge of the
CONVST
signal, t
13
. This is the
minimum acquisition time required of the track-and-hold in
order to maintain 8-bit performance. Figure 13 shows the typical
performance of the AD7825 when channel hopping for various
acquisition times. These results were obtained using an external
reference and internal V
MID
while channel hopping between
V
IN1
and V
IN4
with 0 V on Channel 4 and 0.5 V on Channel 1.
ACQUISITION TIME – ns
8
5
500
10
200
E
100
50
40
30
20
15
7.5
7
6.5
6
5.5
8.5
Figure 13. Effective Number of Bits vs. Acquisition Time
for the AD7825
The on-chip track-and-hold can accommodate input frequen-
cies to 10 MHz, making the AD7822, AD7825, and AD7829
ideal for subsampling applications. When the AD7825 is con-
verting a 10 MHz input signal at a sampling rate of 2 MSPS,
the effective number of bits typically remains above seven,
corresponding to a signal-to-noise ratio of 42 dBs as shown
in Figure 14.
INPUT FREQUENCY – MHz
50
38
0.2
10
1
S
3
4
5
6
8
48
46
44
42
40
F
SAMPLE
= 2MHz
Figure 14. SNR vs. Input Frequency on the AD7825
POWER-UP TIMES
The AD7822/AD7825/AD7829 have a 1
μ
s power-up time
when using an external reference and a 25
μ
s power-up time
when using the on-chip reference. When V
DD
is first connected,
the AD7822, AD7825, and AD7829 are in a low current mode
of operation. Ensure that the
CONVST
line is not floating when
V
DD
is applied, as this could put the AD7822/AD7825/AD7829
into an unknown state. In order to carry out a conversion the
AD7822, AD7825, and AD7829 must first be powered up. The
AD7829 is powered up by a rising edge on the
CONVST
pin
and a conversion is initiated on the falling edge of
CONVST
.
Figure 15 shows how to power up the AD7829 when V
DD
is first
connected or after the AD7829 has been powered down using
the
CONVST
pin when using either the on-chip, or an external,
reference. When using an external reference, the falling edge of
CONVST
may occur before the required power-up time has
elapsed; however, the conversion will not be initiated on the fall-
ing edge of
CONVST
but rather at the moment when the part
has completely powered up, i.e., after 1
μ
s. If the falling edge of
CONVST
occurs after the required power-up time has elapsed,
then it is upon this falling edge that a conversion is initiated.
When using the on-chip reference, it is necessary to wait the
required power-up time of approximately 25
μ
s before initiating
a conversion; i.e., a falling edge on
CONVST
may not occur
before the required power-up time has elapsed, when V
DD
is
first connected or after the AD7829 has been powered down
using the
CONVST
pin as shown in Figure 15.
V
DD
t
POWER-UP
1
m
s
CONVST
V
DD
CONVST
t
POWER-UP
25
m
s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
ON-CHIP REFERENCE
Figure 15. AD7829 Power-Up Time
相關(guān)PDF資料
PDF描述
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