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AD7823
–3–
REV. B
TIMING CHARACTERISTICS
1, 2
Parameter
V
DD
= 5 V 10%
V
DD
= 3 V 10%
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
t
53
t
63
t
73
t
83, 4
5
20
25
25
5
10
5
20
10
1
5
20
25
25
5
10
5
20
10
1
μ
s (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
μ
s (max)
Conversion Time Mode 1 Operation (High Speed Mode)
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
CONVST
Rising Edge to SCLK Rising Edge Set-Up Time
SCLK Rising Edge to D
OUT
Data Valid Delay
Data Hold Time after Rising Edge SCLK
Bus Relinquish Time After Falling Edge of SCLK
t
POWERUP
Power-Up Time
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V
±
10% and
0.4 V or 2 V for V
= 3 V
±
10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t
8
, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40 C to +125 C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(
CONVST
, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(D
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
(V
IN +
, V
IN –
) . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150
°
C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . +125
°
C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . +50
°
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260
°
C
I
OL
200mA
I
200 A
1.6V
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160
°
C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220
°
C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206
°
C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity
Error
Temperature
Range
Branding
Information
Package
Option*
Model
AD7823YN
AD7823YR
AD7823YRM
±
1 LSB
±
1 LSB
±
1 LSB
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
N-8
SO-8
RM-8
C2Y
*N = plastic DIP; RM = microSOIC; SO = small outline IC (SOIC).