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參數(shù)資料
| 型號(hào)： | AD7823YRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SRL 2.7-5.5V 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)偽差分，單極 |
AD7823
–6–
REV. C
CIRCUIT DESCRIPTION
Converter Operation
The AD7823 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Figures
4 and 5 below show simplified schematics of the ADC. Figure 4
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in Position A; the comparator is held in a balanced condi-
tion; and the sampling capacitor acquires the signal on VIN+.
VDD/3
VIN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW2
A
SW1
B
VIN–
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5) SW2 will
open, and SW1 will move to Position B causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor in order to bring the com-
parator back into a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 11 shows the ADC
transfer function.
VDD/3
VIN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
A
SW1
B
VIN–
Figure 5. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7823.
The serial interface is implemented using two wires; the rising
edge of
CONVST enables the serial interface—see Serial
Interface section for more details. VREF is connected to a well
decoupled VDD pin to provide an analog input range of 0 V to
VDD. When VDD is first connected, the AD7823 powers up in
a low current mode, i.e., power-down. A rising edge on the
CONVST input will cause the part to power up—see Operating
Modes. If power consumption is of concern, the automatic power-
down at the end of a conversion should be used to improve
power performance. See Power vs. Throughput Rate section of
the data sheet.
DOUT
SCLK
VREF
AGND
VDD
VIN+
VIN–
CONVST
SUPPLY
2.7V TO 5.5V
0V TO VREF
INPUT
AD7823
0.1 F
TWO-WIRE
SERIAL
INTERFACE
C/ P
10 F
Figure 6. Typical Connection Diagram
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7823. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125
. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN+
C1
3.5pF
R1
125
VDD/3
D2
D1
C2
4pF
CONVERT PHASE – SWITCH OPEN
ACQUISITION PHASE – SWITCH CLOSED
Figure 7. Equivalent Analog Input Circuit
The analog input of the AD7823 is made up of a pseudo dif-
ferential pair, VIN+ pseudo differential with respect to VIN–. The
signal is applied to VIN+ but in the pseudo differential scheme
the sampling capacitor is connected to VIN– during conversion—
see Figure 8. This input scheme can be used to remove offsets
that exist in a system. For example, if a system had an offset of
0.5 V, the offset could be applied to VIN– and the signal applied
to VIN+. This has the effect of offsetting the input span by 0.5 V.
It is only possible to offset the input span when the reference volt-
age (VREF) is less than VDD – VOFFSET.
VDD/3
VIN+
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
VIN–
CHARGE
REDISTRIBUTION
DAC
VOFFSET
VIN(+)
VOFFSET
Figure 8. Pseudo Differential Input Scheme
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