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參數(shù)資料
| 型號： | AD7828KP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT LC2MOS 8CH 28-PLCC |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 3 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7824/AD7828
–8–
REV. F
UNIPOLAR OPERATION
The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
AD7824*
AD7828*
AIN1
GND
VDD
VREF (+)
VREF (–)
47 F
0.1 F
VIN
0V TO 5V
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
DB7
DB0
VREF
5V
Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation
11111111
11111110
11111101
00000011
00000010
00000001
00000000
FULL-SCALE
TRANSITION
OUTPUT
CODE
1LSB 2LSB 3LSB
FS – 1LSB
FS
0
AIN, INPUT VOLTAGE – LSB
1LSB =
FS
256
Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (VIN) so that only
positive voltages appear at AIN1. The closed loop transfer func-
tion of the op amp for the resistor values shown is given below:
AIN
V
Volts
IN
1
=
()
25
0625
..
The analog input range is
±4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
AD7824*
AD7828*
AIN1
GND
VDD
VREF (+)
VREF (–)
47 F
0.1 F
VIN
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
DB7
DB0
5V
AD544
5V
40k
27k
25k
12k
Figure 12. AD7824/AD7828 Bipolar
±4 V Operation
AIN, INPUT VOLTAGE – LSB
11111111
11111110
00000000
0V
OUTPUT
CODE
01111111
01111110
00000010
00000001
10000001
10000000
10000010
11111101
+FS
2
–FS
2
+ 1LSB
FS = 8V
1LSB = FS/256
Figure 13. Ideal Input/Output Transfer Characteristic for
±4 V Operation
TIMING AND CONTROL
The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (
CS) and Read (RD). A READ
operation brings
CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e.,
CS and RD are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.
Table I. Truth Table for Input Channel Selection
AD7824
AD7828
A1
A0
A2
A1
A0
Channel
00
0
AIN1
01
00
1
AIN2
10
01
0
AIN3
11
01
1
AIN4
10
0
AIN5
10
1
AIN6
11
0
AIN7
11
1
AIN8
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