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參數(shù)資料
| 型號(hào)： | AD7840JN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT LC2MOS VOUT 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 2.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 400k |
AD7840
REV. B
–7–
Table III. Parallel Mode Truth Table
CS
WR
LDAC
Function
HX
H
}Both Latches Latched
XH
H
L
H
Input Latch Transparent
HH
L
}
Input Latch Latched
H
X
L
DAC Latch Transparent
X
H
L
Analog Output Updated
ff
L
Input Latch Transparent
DAC Latch Data Transfer Inhibited
L
g
L
}Input Latch Is Latched
g
L
DAC Latch Data Transfer Occurs
X = Don’t Care
Figure 6. Parallel Mode Timing Diagram
Figure 7. AD7840 Simplified Parallel Input Control Logic
Serial Data Format
The serial data format is selected for the AD7840 by connecting
the CS/SERIAL line to –5 V. In this case, the WR/SYNC,
D13/SDATA, D12/SCLK, D11/FORMAT and D10/JUSTIFY
pins all assume their serial functions. The unused parallel inputs
should not be left unconnected to avoid noise pickup. Serial
data is loaded to the input latch under control of SCLK, SYNC
and SDATA. The AD7840 expects a 16-bit stream of serial data
on its SDATA input. Serial data must be valid on the falling
edge of SCLK. The SYNC input provides the frame synchroni-
zation signal which tells the AD7840 that valid serial data will
be available for the next 16 falling edges of SCLK. Figure 8
shows the timing diagram for serial data format.
Figure 8. Serial Mode Timing Diagram
Although 16 bits of data are clocked into the AD7840, only 14
bits go into the input latch. Therefore, two bits in the stream are
don’t cares since their value does not affect the input latch data.
The order and position in which the AD7840 accepts the 14 bits
of input data depends upon the FORMAT and JUSTIFY in-
puts. There are four different input data modes which can be
chosen (see Table I in the Pin Function Description section).
The first mode (M1) assumes that the first two bits of the input
data stream are don’t cares, the third bit is the LSB and the last
(or 16th bit) is the MSB. This mode is chosen by tying both the
FORMAT and JUSTIFY pins to a logic 0. The second mode
(M2; FORMAT = 0, JUSTIFY = 1) assumes that the first bit in
the data stream is the LSB, the fourteenth bit is the MSB and
the last two bits are don’t cares. The third mode (M3;
FORMAT= 1, JUSTIFY 0) assumes that the first two bits in
the stream are again don’t cares, the third bit is now the MSB
and the sixteenth bit is the LSB. The final mode (M4; FOR-
MAT = 1, JUSTIFY= 1) assumes that the first bit is the MSB,
the fourteenth bit is the LSB and the last two bits of the stream
are don’t cares.
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| AD7840-JN | 制造商: 功能描述: 制造商:undefined 功能描述: |
| AD7840JNZ | 功能描述:IC DAC 14BIT LC2MOS LP 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD7840JNZ | 制造商:Analog Devices 功能描述:IC 14-BIT DAC |
| AD7840JP | 功能描述:IC DAC 14BIT LC2MOS VOUT 28PLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7840JP-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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