參數(shù)資料
型號: AD7843ARQZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 20/21頁
文件大?。?/td> 0K
描述: IC ADC 12BIT TOUCHSCREEN 16-QSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
評估套件: 可供
數(shù)據(jù)接口: 串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 125k
電壓基準(zhǔn): 外部
電源電壓: 2.2 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
配用: EVAL-AD7843EBZ-ND - BOARD EVAL FOR AD7843
AD7843
Rev. B | Page 7 of 20
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00…000) to
(00…001) from the ideal, that is, AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (111…110) to
(111…111) from the ideal (VREF 1 LSB) after the offset error
has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier enters the acquisition phase on
the fifth falling edge of DCLK after the START bit has been
detected. Three DCLK cycles are allowed for the track-and-hold
acquisition time. The input signal is fully acquired to the 12-bit
level within this time even with the maximum specified DCLK
frequency. See the Analog Input section for more details.
On Resistance
This is a measure of the ohmic resistance between the drain and
source of the switch drivers.
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