參數(shù)資料
型號(hào)： AD7843ARUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/21頁(yè)
文件大小： 0K
描述： IC ADC 12BIT TOUCHSCREEN 16TSSOP
標(biāo)準(zhǔn)包裝： 96
類型： 電阻
觸摸面板接口： 4 線
輸入數(shù)/鍵： 1 TSC
分辨率（位）： 12 b
評(píng)估套件： 可供
數(shù)據(jù)接口： 串行
數(shù)據(jù)速率/采樣率 (SPS，BPS)： 125k
電壓基準(zhǔn)： 外部
電源電壓： 2.2 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
配用： EVAL-AD7843EBZ-ND - BOARD EVAL FOR AD7843
AD7843
Rev. B | Page 12 of 20
ANALOG INPUT
Figure 19 shows an equivalent circuit of the analog input
structure of the AD7843, which contains a block diagram of the
input multiplexer, the differential input of the ADC, and the
differential reference.
Table 5 shows the multiplexer address corresponding to each
analog input, both for the SER/DFR bit in the control register
set high and low. The control bits are provided serially to the
device via the DIN pin. For more information on the control
register, see the Control Register section.
When the converter enters hold mode, the voltage difference
between the +IN and IN inputs (see Figure 19) is captured on
the internal capacitor array. The input current on the analog
inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling
capacitor (typically 37 pF). Once the capacitor is fully charged,
there is no further input current. The rate of charge transfer
from the analog source to the converter is a function of
conversion rate.
Acquisition Time
The track-and-hold amplifier enters tracking mode on the
falling edge of the fifth DCLK after the START bit us detected
(see Figure 24). The time required for the track-and-hold
amplifier to acquire an input signal depends on how quickly the
37 pF input capacitance is charged. With zero source impedance
on the analog input, three DCLK cycles are always sufficient to
acquire the signal to the 12-bit level. With a source impedance
RIN on the analog input, the actual acquisition time required is
calculated using the formula:
(
)
pF
37
100
4
.
8
×
+
×
=
IN
ACQ
R
t
where RIN is the source impedance of the input signal and 100
and 37 pF is the input RC value. Depending on the frequency of
DCLK used, three DCLK cycles may or may not be sufficient to
acquire the analog input signal with various source impedance
values.
02144-B
-019
VCC
X+
X+ Y+
REF
EXT
X– Y– GND
X+
Y+
IN3
IN4
X–
Y+
Y–
ON-CHIP SWITCHES
4-TO-1
MUX
3-TO-1
MUX
3-TO-1
MUX
IN+
IN– REF–
REF+
ADC CORE
DATA OUT
Figure 19. Equivalent Analog Input Circuit
Table 5. Analog Input, Reference, and Touch Screen Control
A21
A11
A01
SER/DFR
Analog Input
X Switches
Y Switches
+REF2
–REF2
0
1
X+
OFF
ON
VREF
GND
0
1
0
1
IN3
OFF
VREF
GND
1
0
1
Y+
ON
OFF
VREF
GND
1
0
1
IN4
OFF
VREF
GND
0
1
0
X+
OFF
ON
Y+
Y
1
0
1
0
Y+
ON
OFF
X+
X
1
0
Outputs Identity Code, 1000 0000 0000
1 All remaining configurations are invalid addresses.
2 Internal node not directly accessible by the user.
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