參數(shù)資料
型號: AD7846JP
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC DAC 16BIT LC2MOS VOUT 28PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 7µs
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 100mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 143k
AD7846
Rev. G | Page 16 of 24
MICROPROCESSOR INTERFACING
AD7846-TO-8086 INTERFACE
Figure 26 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used in
this circuit because LDAC is permanently tied to 0 V. AD0 to
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0 to DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is 0xD000.
AD7846*
+5V
DATA BUS
CS
LDAC
CLR
R/W
DB0 TO DB15
16-BIT
LATCH
8086
ALE
DEN
RD
WR
AD0 TO AD15
ADDRESS
DECODE
ADDRESS BUS
08
49
0-
0
28
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 26. AD7846-to-8086 Interface Circuit
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure 27,
a 16-bit word is loaded to the input latches of each of the DACs
in sequence. Then, with one instruction to the appropriate
address, CS4 (that is, LDAC) is brought low, updating all the
DACs simultaneously.
+5V
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
16-BIT
LATCH
ADDRESS
DECODE
ADDRESS BUS
AD7846*
CS
LDAC
R/W
DB0 TO DB15
8086
ALE
DEN
RD
WR
AD0 TO AD15
CLR
+5V
CLR
+5V
AD7846*
CS
LDAC
R/W
DB0 TO DB15
AD7846*
CS
LDAC
R/W
DB0 TO DB15
0849
0-
0
29
Figure 27. AD7846-to-8086 Interface: Multiple DAC System
AD7846-TO-MC68000 INTERFACE
Interfacing between the AD7846 and MC68000 is accomplished
using the circuit of Figure 28. The following routine writes data
to the DAC latches and then outputs the data via the DAC latch.
1000
MOVE.W
#W,
D0
The desired DAC data,
W, is loaded into
Data Register 0. W
may be any value
between 0 and 65535
(decimal) or 0 and
FFFF (hexadecimal).
MOVE.W
D0,
$E000
The data, W, is
transferred between
D0 and the DAC
register.
MOVE.W
TRAP
#228,
D7
#14
Control is returned
to the System Monitor
using these two
instructions.
AD7846*
+5V
DATA BUS
CS
LDAC
CLR
R/W
MC68000
DS
DTACK
R/W
A1 TO A23
ADDRESS
DECODE
ADDRESS BUS
D0 TO D15
DB0 TO DB15
0
84
90
-03
0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 28. AD7846-to-MC68000 Interface
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