參數(shù)資料
型號: AD7853BRZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 20/34頁
文件大小: 0K
描述: IC ADC 12BIT SRL 200KSPS 24SOIC
標準包裝: 1,000
位數(shù): 12
采樣率(每秒): 200k
數(shù)據(jù)接口: 8051,QSPI?,串行,SPI? µP
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 33mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極;1 個偽差分,雙極
REV. B
–27–
AD7853/AD7853L
CONFIGURING THE AD7853/AD7853L
AD7853/AD7853L as a Read-Only ADC
The AD7853/AD7853L contains fourteen on-chip registers
which can be accessed via the serial interface. In the majority of
applications it will not be necessary to access all of these regis-
ters. Figure 38 outlines a flowchart of the sequence which is
used to configure the AD7853/AD7853L as a Read-Only ADC.
In this case there is no writing to the on-chip registers and only
the conversion result data is read from the part. Interface Mode
1 cannot be used in this case as it is necessary to write to the
control register to set Interface Mode 1. Here the CLKIN signal
is applied directly after power-on, the CLKIN signal must be
present to allow the part to perform a calibration. This auto-
matic calibration will be completed approximately 32 ms after
the AD7853 has powered up (4 MHz CLK).
SERIAL
INTERFACE
MODE
?
POWER-ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
DIN CONNECTED TO DGND
NO
YES
START
WAIT FOR BUSY SIGNAL
TO GO LOW
PULSE
CONVST PIN
READ
DATA
DURING
CONVERSION
?
WAIT APPROXIMATLY 200ns
AFTER
CONVST RISING EDGE
APPLY
SYNC (IF REQUIRED), SCLK AND READ
CONVERSION RESULT ON DOUT PIN
PULSE
CONVST PIN
SYNC AUTOMATICALLY GOES LOW
AFTER
CONVST RISING EDGE
SCLK AUTOMATICALLY ACTIVE, READ
CONVERSION RESULT ON DOUT PIN
4, 5
2, 3
Figure 40. Flowchart for Setting Up and Reading from the AD7853/AD7853L
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