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參數(shù)資料
| 型號(hào)： | AD7853LARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24SSOP |
| 標(biāo)準(zhǔn)包裝： | 59 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極 |
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REV. B
–18–
AD7853/AD7853L
is powered down and IDD is 400 A typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7853 circuitry is pow-
ered down. It also allows the AD7853 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the
SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the
SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7853) to achieve better power
performances, then the
SLEEP pin should be tied logic low.
If the power-down options are to be selected in software only,
then the
SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
A typical connection diagram for a low power application is
shown in Figure 23 (AD7853L is the low power version of the
AD7853).
INPUT FREQUENCY – kHz
–78
–80
–90
0
100
PSRR
–
dB
20
40
60
80
–82
–84
–86
5.0V
3.3V
AVDD = DVDD = 3.3V/5.0V,
100mV p-p SINE WAVE ON AVDD
–88
Figure 22. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7853 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the
SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7853 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and IDD is 1
A typ. If a partial power-
down is selected, then all the on-chip circuitry except the reference
AVDD DVDD
AIN(+)
AIN(–)
AMODE
CREF1
CREF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REFIN/REFOUT
POLARITY
AD7853L
0.1 F
10 F
DVDD
UNIPOLAR RANGE
0.1 F
0.01 F
SERIAL MODE
SELECTION BITS
MASTER CLOCK INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1 F
CAL
0.01 F
INTERNAL
REFERENCE
0V TO 2.5V
INPUT
1.8MHz OSCILLATOR
SERIAL CLOCK INPUT
100kHz PULSE
GENERATOR
DIN AT DGND
=> NO WRITING
TO DEVICE
AUTO POWER-
DOWN AFTER
CONVERSION
THREE-WIRE
MODE
SELECTED
LOW POWER
C/ P
AUTO CAL ON
POWER-UP
CURRENT, I = 1.5mA TYP
REF-192
ANALOG SUPPLY
+3V
OPTIONAL EXTERNAL
REFERENCE
Figure 23. Typical Low Power Circuit
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| AD7853LARSZ-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7853LARZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7853LARZ-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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