參數(shù)資料
型號(hào)： AD7856KR-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/32頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 8CH 5V 24-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 14
采樣率（每秒）： 285k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)偽差分，單極
AD7856
–14–
REV. A
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
READ
OPERATION
OR
ABORT
?
FINISHED
YES
NO
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is approxi-
mately 0010 0000 0000 0000. This is not an exact value, but
the value in the offset register should be close to this value. Each
of the 14 data bits in the offset register is binary weighted: the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB, which has a weighting of 0.0006%.
This gives a resolution of approximately
±0.0006% of V
REF.
More accurately the resolution is
±(0.05 × V
REF )/2
13 volts =
±0.015 mV, with a 2.5 V reference. The maximum specified
offset that can be compensated for is
±3.75% of the reference
voltage but is typically
±5%, which equates to ±125 mV with a
2.5 V reference and
±250 mV with a 5 V reference.
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V, what code needs to be written to the
offset register to compensate for the offset?
A. 2.5 V reference implies that the resolution in the offset regis-
ter is 5%
× 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range. Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range for which the gain register can compensate is
1.01875 times the reference voltage; the minimum input range
is 0.98125 times the reference voltage.
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