參數(shù)資料
型號(hào): AD7858LARSZ
廠商: Analog Devices Inc
文件頁數(shù): 18/32頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 8CHAN SRL 24SSOP
標(biāo)準(zhǔn)包裝: 59
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: 8051,QSPI?,串行,SPI? µP
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 33mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極;4 個(gè)偽差分,單極
AD7858/AD7858L
REV. B
–25–
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2 which is the SPI/QSPI interface mode. Here the
SYNC
input is active low and may be pulsed or tied permanently low.
If
SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, otherwise with a
pulsed
SYNC input a continuous SCLK may be applied pro-
vided
SYNC is low for only 16 SCLK cycles. In Figure 33 the
SYNC going low disables the three-state on the DOUT pin.
The first falling edge of the SCLK after the
SYNC going low
clocks out the first leading zero on the DOUT pin. The DOUT
pin is three-stated again a time t12 after the SYNC goes high.
With the DIN pin the data input has to be set up a time t7 be-
fore the SCLK rising edge as the part samples the input data on
the SCLK rising edge in this case. If resetting the interface is
required, the
SYNC must be taken high and then low.
t11
t12
16
6
5
4
3
2
1
t10
t8
t6
t9
t8
t6
t3
t5
THREE-STATE
DB0
DB10
DB11
DB12
DB13
DB14
DB15
DB14
DB13
DB12
DB11
DB10
DB0
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
t3 = –0.4tSCLK MIN (NONCONTINUOUS SCLK) 0.4tSCLK ns MIN/MAX (CONTINUOUS SCLK),
t6 = 75/115ns MAX (5V/3V), t7 = 40/60ns MIN (5V/3V), t8 = 20/30ns MIN (5V/3V),
t11 = 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4tSCLK ns MIN/MAX
(CONTINUOUS SCLK) (5V/3V)
DB15
t7
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation
with DIN Input, DOUT Output, and
SYNC Input
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