- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10177 > AD7863ARSZ-2REEL (Analog Devices Inc)IC ADC 14BIT DUAL 2CHAN 28SSOP PDF資料下載
參數(shù)資料
| 型號： | AD7863ARSZ-2REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 2CHAN 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 175k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 94.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極 |
AD7863
Rev. B | Page 13 of 24
OPERATING MODES
MODE 1 OPERATION
Normal Power, High Sampling Performance
The timing diagram in Figure 7 is for optimum performance in
operating Mode 1 where the falling edge of CONVST starts
conversion and puts the track-and-hold amplifiers into their
hold mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 5.2 μs max after the falling edge of CONVST and new
data from this conversion is available in the output latch of the
AD7863. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion accesses the result from Channel A (VA1 and VA2,
respectively). The third and fourth read pulses, after the second
conversion and A0 high, access the result from Channel B (VB1
and VB2, respectively). Data is read from the part via a 14-bit
parallel data bus with standard CS and RD signals. This data
read operation consists of a negative going pulse on the CS pin
combined with two negative going pulses on the RD pin (while
the CS is low), accessing the two 14-bit results. For the fastest
throughput rate the read operation takes 100 ns. The read
operation must be complete at least 400 ns before the falling
edge of the next CONVST and this gives a total time of 5.7 μs
for the full throughput time (equivalent to 175 kHz). This mode
of operation should be used for high sampling applications.
MODE 2 OPERATION
Power-Down, Auto-Sleep After Conversion
The timing diagram in Figure 11 is for optimum performance
in operating Mode 2 where the part automatically goes into
sleep mode once BUSY goes low after conversion and wakes up
before the next conversion takes place. This is achieved by
keeping CONVST low at the end of the second conversion,
whereas it was high at the end of the second conversion for
Mode 1 operation.
The operation shown in Figure 11 shows how to access data
from both Channel A and Channel B, followed by the auto sleep
mode. One can also set up the timing to access data from
Channel A only or Channel B only (see the Read Options
section) and then go into auto sleep mode. The rising edge of
CONVST wakes up the part. This wake-up time is 4.8 μs when
using an external reference and 5 ms when using the internal
reference, at which point the track-and-hold amplifiers go into
their hold mode, provided the CONVST has gone low. The
conversion takes 5.2 μs after this giving a total of 10 μs (external
reference, 5.005 ms for internal reference) from the rising edge
of CONVST to the conversion being complete, which is
indicated by the BUSY going low.
Note that because the wake-up time from the rising edge of
CONVST is 4.8 μs, if the CONVST pulse width is greater than
5.2 μs the conversion takes more than the 10 μs (4.8 μs wake-up
time + 5.2 μs conversion time) shown in Figure 11 from the
rising edge of CONVST. This is because the track-and-hold
amplifiers go into their hold mode on the falling edge of
CONVST and the conversion does not complete for a further
5.2 μs. In this case, the BUSY is the best indicator of when the
conversion is complete. Even though the part is in sleep mode,
data can still be read from the part.
The read operation is identical to that in Mode 1 operation and
must also be complete at least 400 ns before the falling edge of
the next CONVST to allow the track-and-hold amplifiers to
have enough time to settle. This mode is very useful when the
part is converting at a slow rate because the power consumption
is significantly reduced from that of Mode 1 operation.
A1
VA2
CONVST
BUSY
A0
CS
RD
DATA
* WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 4.8s.
** WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms.
4.8s*/5ms**
WAKE-UP TIME
t3
tCONV = 5.2s
VB1
VB2
t8
tACQ
06
41
1-
0
11
Figure 11. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72245LB15PF | IC FIFO 1024X18 SYNC 15NS 64QFP |
| MS3102R16-11S | CONN RCPT 2POS BOX MNT W/SCKT |
| MS27467E17A35P | CONN PLUG 55POS STRAIGHT W/PINS |
| VE-J5K-MX-S | CONVERTER MOD DC/DC 40V 75W |
| MS27484T16B99P | CONN PLUG 23POS STRAIGHT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7863ARSZ-2REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 175 kSPS 14-Bit ADC |
| AD7863ARSZ-2REEL7 | 功能描述:IC ADC 14BIT DUAL 2CHAN 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7863ARSZ-2REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 175 kSPS 14-Bit ADC |
| AD7863ARSZ-3 | 功能描述:IC ADC 14BIT DUAL 2CHAN 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7863ARSZ-31 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 175 kSPS 14-Bit ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。