參數(shù)資料
型號(hào)： AD7863BR-3
廠商： Analog Devices Inc
文件頁數(shù)： 19/24頁
文件大?。?/td> 0K
描述： IC ADC 14BIT DUAL 2CH 28-SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 175k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 94.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
AD7863
Rev. B | Page 4 of 24
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
REF IN Input Voltage Range
2.375 to 2.625
V
2.5 V ± 5%
REF IN Input Current
±100
μA max
REF OUT Output Voltage
2.5
V nom
REF OUT Error @ 25°C
±10
mV max
REF OUT Error TMIN to TMAX
±20
mV max
REF OUT Temperature Coefficient
25
ppm/°C typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
V min
VDD = 5 V ± 5%
Input Low Voltage, VINL
0.8
V max
VDD = 5 V ± 5%
Input Current, IIN
±10
μA max
Input Capacitance, CIN5
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
4.0
V min
ISOURCE = 200 μA
Output Low Voltage, VOL
0.4
V max
ISINK = 1.6 mA
DB11 to DB0
Floating-State Leakage Current
±10
μA max
Floating-State Capacitance5
10
pF max
Output Coding
AD7863-10, AD7863-3
Twos complement
AD7863-2
Straight (natural) binary
CONVERSION RATE
Conversion Time
Mode 1 Operation
5.2
μs max
For both channels
Mode 2 Operation6
10.0
μs max
For both channels
Track/Hold Acquisition Time4, 7
0.5
μs max
POWER REQUIREMENTS
VDD
5
V nom
±5% for specified performance
IDD
Normal Mode (Mode 1)
AD7863-10
18
mA max
AD7863-3
16
mA max
AD7863-2
11
mA max
Power-Down Mode (Mode 2)
IDD @ 25°C8
20
μA max
40 nA typ. Logic inputs = 0 V or VDD
Power Dissipation
Normal Mode (Mode 1)
AD7863-10
94.50
mW max
VDD = 5.25 V, 70 mW typ
AD7863-3
84
mW max
VDD = 5.25 V, 70 mW typ
AD7863-2
57.75
mW max
VDD = 5.25 V, 45 mW typ
Power-Down Mode @ 25°C
105
μW max
210 nW typ, VDD = 5.25 V
1 Temperature ranges are as follows: A Version and B Version, 40°C to +85°C.
2 Sample tested during initial release.
3 Applies to Mode 1 operation. See Operating Modes section.
4 See Terminology section.
5 Sample tested @ 25°C to ensure compliance.
6 This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of
CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if
the CONVST pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs.
7 Performance measured through full channel (multiplexer, SHA, and ADC).
8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure
shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in
the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the VDD pin and
2 × 0.1 μF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane.
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