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參數(shù)資料
| 型號： | AD7864ASZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT DUAL 4CH 44-MQFP |
| 標準包裝： | 800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 520k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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AD7864
Rev. D | Page 17 of 28
Successive read operations access the remaining conversion
results in an ascending channel order. Each read operation
increments the output data register pointer. The read operation
that accesses the last conversion result causes the output data
register pointer to be reset so that the next read operation accesses
the first conversion result again. This is shown in Figure 10,
wherein the fifth read after BUSY goes low accessing the result
of the conversion on VIN1. Thus, the output data registers act as
a circular buffer in which the conversion results are continually
accessible. The FRSTDATA signal goes high when the first
conversion result is available.
Data is enabled onto the data bus (DB0 to DB11) using CS and
RD. Both CS and RD have the same functionality as described
in the previous section. There are no restrictions or performance
implications associated with the position of the read operations
after BUSY goes low. The only restriction is that there is minimum
time between read operations. Notice that the quiet time must
be allowed before the start of the next conversion.
USING AN EXTERNAL CLOCK
The logic input INT/EXT CLK allows the user to operate the
AD7864 using the internal clock oscillator or an external clock.
To achieve optimum performance on the AD7864, use the internal
clock. The highest external clock frequency allowed is 5 MHz.
This means a conversion time of 2.6 μs compared to 1.65 μs
when using the internal clock. In some instances, however, it
may be useful to use an external clock when high throughput
rates are not required. For example, two or more AD7864s can
be synchronized by using the same external clock for all
devices. In this way, there is no latency between output logic
signals like EOC due to differences in the frequency of the
internal clock oscillators.
shows how the various logic
outputs are synchronized to the CLK signal. Each conversion
requires 14 clocks. The output data register pointer is reset to
point to the first register location on the falling edge of the 12th
clock cycle of the first conversion in the conversion sequence—
see the
section. At this
point, the logic output FRSTDATA goes logic high. The result of
the first conversion transfers to the output data registers on the
falling edge of the 13th clock cycle. The FRSTDATA signal is
reset on the falling edge of the 13th clock cycle of the next
conversion, that is, when the result of the second conversion is
transferred to its output data register. As mentioned previously,
the pointer is incremented by the rising edge of the
RD signal if
the result of the next conversion is available. The EOC signal
goes logic low on the falling edge of the 13th clock cycle and is
reset high again on the falling edge of the 14th clock cycle.
CONVST
BUSY
EOC
RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 45 6 7 89 10 11 12 13 14 1 213 14
CLK
FRSTDATA
FIRST CONVERSION
COMPLETE
LAST CONVERSION
COMPLETE
01
34
1-
01
1
Figure 11. Using an External Clock
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7864ASZ-1REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864ASZ-2 | 功能描述:IC ADC 12BIT PAR 520K 4CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7864ASZ-22 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864ASZ-2REEL | 功能描述:IC ADC 12BIT PAR 520K 4CH 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7864ASZ-2REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
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