TIMING CHARACTERISTICS1, 2 Parameter A, B, Y Versions Unit Test Conditions/Comments <" />
參數(shù)資料
型號(hào)： AD7865BSZ-1REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/19頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 4CHAN 5V 44-MQFP
標(biāo)準(zhǔn)包裝： 800
位數(shù)： 14
采樣率（每秒）： 350k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 160mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，雙極
REV. B
AD7865
–4–
TIMING CHARACTERISTICS1, 2
Parameter
A, B, Y Versions
Unit
Test Conditions/Comments
tCONV
2.4
s max
Conversion Time, Internal Clock
3.2
s max
Conversion Time, External Clock (5 MHz)
tACQ
0.35
s max
Acquisition Time
tBUSY
No. of Channels
Selected Number of Channels Multiplied by tCONV
× (tCONV)
s max
tWAKE-UP—External VREF
3
1
s max
STBY Rising Edge to CONVST Rising Edge
t1
35
ns min
CONVST Pulsewidth
t2
70
ns min
CONVST Rising Edge to BUSY Rising Edge
Read Operation
t3
0
ns min
CS to RD Setup Time
t4
0
ns min
CS to RD Hold Time
t5
35
ns min
Read Pulsewidth
t6
4
35
ns max
Data Access Time after Falling Edge of
RD, V
DRIVE = 5 V
40
ns max
Data Access Time after Falling Edge of
RD, V
DRIVE = 3 V
t7
5
ns min
Bus Relinquish Time after Rising Edge of
RD
30
ns max
t8
15
ns min
Time Between Consecutive Reads
t9
120
ns min
EOC Pulsewidth
180
ns max
t10
70
ns max
RD Rising Edge to FRSTDATA Edge (Rising or Falling)
t11
15
ns max
EOC Falling Edge to FRSTDATA Falling Delay
t12
0
ns min
EOC to RD Delay
Write Operation
t13
20
ns min
WR Pulsewidth
t14
0
ns min
CS to WR Setup Time
t15
0
ns min
WR to CS Hold Time
t16
5
ns min
Input Data Setup Time of Rising Edge of
WR
t17
5
ns min
Input Data Hold Time
External Clock
t18
200
ns min
CONVST Falling Edge to CLK Rising Edge
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 6, 7 and 8.
3Refer to the Standby Mode Operation section. The MAX specification of 1
s is valid when using a 0.1 F decoupling capacitor on the V
REF pin.
4Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
50pF
TO OUTPUT
PIN
1.6V
400 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(VDD = 5 V
5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications
TMIN to TMAX unless otherwise noted.)
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