TA = T
參數(shù)資料
型號: AD7877ACBZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 42/45頁
文件大?。?/td> 0K
描述: IC CTRLR TOUCH SCREEN 25-WLCSP
標準包裝: 10,000
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
評估套件: 可供
數(shù)據(jù)接口: 串行,SPI?
數(shù)據(jù)速率/采樣率 (SPS,BPS): 125k
電壓基準: 外部,內部
電源電壓: 2.7 V ~ 5.25 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 25-UFBGA,WLCSP
供應商設備封裝: 25-WLCSP
包裝: 帶卷 (TR)
配用: EVAL-AD7877EBZ-ND - BOARD EVALUATION FOR AD7877
Data Sheet
AD7877
Rev. D | Page 5 of 44
TIMING SPECIFICATIONS
TA = TMIN to TMAX, unless otherwise noted, VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input
signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
fDCLK1
10
kHz min
20
MHz max
t1
16
ns min
CS falling edge to first DCLK rising edge
t2
20
ns min
DCLK high pulse width
t3
20
ns min
DCLK low pulse width
t4
12
ns min
DIN setup time
t5
12
ns min
DIN hold time
16
ns max
CS falling edge to DOUT, three-state disabled
16
ns max
DCLK falling edge to DOUT valid
16
ns max
CS rising edge to DOUT high impedance
t9
0
ns min
CS rising edge to DCLK ignored
1
Mark/space ratio for the DCLK input is 40/60 to 60/40.
2
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
3
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
TIMING DIAGRAMS
03796-004
DCLK
t1
t2
t3
t5
t4
t6
t7
t9
t8
DIN
MSB
LSB
MSB
LSB
DOUT
1
2
3
15
16
CS
Figure 2. Detailed Timing Diagram
03796-003
200
A
IOL
200
A
IOH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 3. Load Circuit for Digital Output Timing Specifications
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