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參數資料
| 型號： | AD7879-1WARUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 22/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT CTRLR TOUCH 16TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評估套件： | * |
| 數據接口： | I²C，串行 |
| 數據速率/采樣率 (SPS，BPS)： | 105k |
| 電壓基準： | 內部 |
| 電源電壓： | 1.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD7879/AD7889
Rev. C | Page 28 of 40
PM1
PM0
GPIO
EN
GPIO
DAT
GPIO
DIR
GPIO
POL
AVG1 AVG0 MED1 MED0
SW/
RST
FCD3
FCD2
FCD1 FCD0
07667-
030
0
15
SER/
DFR
Figure 31. Control Register 2
CONTROL REGISTER 2
Control Register 2 (Address 0x02) contains the ADC power
management bits, the GPIO settings, the SER/DFR bit (to
choose the single-ended or differential method of touch screen
measurement), the averaging and median filter settings, a bit
that allows resetting of the part, and the first conversion delay
bits. Its power-on default value is 0x4040. See the Detailed
Register Descriptions section for more information about the
control registers.
For information about the averaging and median filter settings,
see the Median and Averaging Filters section. For information
about the GPIO settings, see the GPIO section.
First Conversion Delay (Control Register 2, Bits[3:0])
The first conversion delay (FCD) bits in Control Register 2
program a delay from 128 s (default) up to 4.096 ms before
the first conversion to allow the ADC time to power up. This
delay also occurs before conversion of the X and Y coordinate
channels to allow extra time for screen settling, and after the
last conversion in a sequence to precharge PENIRQ.
Table 22. First Conversion Delay Selection
FCD[3:0]
Delay
0000
128 s
0001
256 s
0010
384 s
0011
512 s
0100
640 s
0101
768 s
0110
896 s
0111
1.024 ms
1000
1.152 ms
1001
1.280 ms
1010
1.536 ms
1011
1.792 ms
1100
2.048 ms
1101
2.560 ms
1110
3.584 ms
1111
4.096 ms
Power Management (Control Register 2, Bits[15:14])
The power management (PM) bits in Control Register 2 allow
the power management features of the ADC to be programmed
(see Table 23). If the PM bits are set to 00, the ADC is in full
shutdown. This setting overrides any setting of the mode bits in
Control Register 1. Power management overrides the ADC modes.
Table 23. Power Management Selection
PM1
PM0
Function
0
Full shutdown; ADC, oscillator, bias, and temp-
erature sensor are turned off. The only way to
exit this mode is to write to the part over the
serial interface and change the PM bits. This
setting overrides any other setting on the
part, including the ADC mode bits.
0
1
The analog blocks to be powered down
depend on the ADC mode setting. In master
mode, the ADC, bias, temperature sensor, and
oscillator are powered down and must wake
up when the user touches the screen. In slave
mode, the ADC and temperature sensor are
powered down when not being used. They
wake up automatically when required. The
oscillator and bias are powered up because
they are needed to measure time. This setting
also applies to the single-conversion mode.
1
0
The ADC, bias, and oscillator are powered up
continuously, irrespective of ADC mode.
1
Same as 01.
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| AD7879ACPZ-RL | 功能描述:IC ADC 12BIT CTLR TOUCH 16LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 觸摸屏控制器 系列:- 標準包裝:96 系列:- 類型:- 觸摸面板接口:- 輸入數/鍵:- 分辨率（位）:- 評估套件:* 數據接口:- 數據速率/采樣率 (SPS，BPS):- 電壓基準:- 電源電壓:- 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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