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參數(shù)資料
| 型號(hào)： | AD7880BN |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT MONO LP 24-DIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 66k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極 |
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AD7880
REV. 0
–9–
MICROPROCESSOR INTERFACING
The AD7880 high speed bus timing allows direct interfacing to
real time digital signal processors, DSPs, as well as modern high
speed, 16-bit microprocessors. Suitable microprocessor inter-
faces are shown in Figures 15 through 20.
AD7880–ADSP-2100 Interface
Figure 15 shows an interface between the AD7880 and the
ADSP-2100. Conversion is initiated using a timer to drive the
CONVST
input asynchronously to the microprocessor. This al-
lows very accurate control of the sampling instant. When con-
version is complete, the AD7880 BUSY line goes high. An
inverter on this BUSY output drives the IRQ line low thus pro-
viding an interrupt to the ADSP-2100 when conversion is com-
pleted. The conversion result is then read from the AD7880 into
the ADSP-2100 with the following instruction:
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 Register and
where ADC is the AD7880 address.
TIMER
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7880*
IRQn
DMRD (RD)
Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102)
Interface
AD7880-ADSP-2101/ADSP-2102 Interface
The interface outlined in Figure 15 also forms the basis for an
interface between the AD7880 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. The instruction used to read a conversion result is as out-
lined for the ADSP-2100.
AD7880-TMS32010 Interface
An interface between the AD7880 and the TMS32010 is shown
in Figure 16. Once again the conversion is initiated using an ex-
ternal timer and the TMS32010 is interrupted when conversion
is completed. The following instruction is used to read the con-
version result from the AD7880:
IN D,ADC
where D is Data Memory Address and
where ADC is the AD7880 address.
PA0
PA2
D15
D0
MEN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
AD7880*
TMS32010
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
EN
BUSY
Figure 16. AD7880–TMS32010 Interface
AD7880–TMS320C25 Interface
Figure 17 shows an interface between the AD7880 and the
TMS320C25. As with the two previous interfaces, conversion is
initiated with a timer, and the processor is interrupted when the
conversion sequence is completed. The TMS320C25 does not
have a separate RD output to drive the AD7880 RD input di-
rectly. This has to be generated from the processor STRB and
R/W outputs with the addition of some logic gates. The RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7880 using the follow-
ing instruction:
IN D,ADC
where D is Data Memory Address and
where ADC is the AD7880 address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
AD7880*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
BUSY
Figure 17. AD7880–TMS320C25 Interface
Some applications may require that the conversion be initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7880 CONVST from the address bus so that
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