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參數(shù)資料
型號: AD7886JP-REEL
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SAMPLING HS 28-PLCC
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 350mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極
AD7886
–4–
REV. B
ORDERING GUIDE
Integral
Temperature
SNR
Nonlinearity
Package
Model1, 2
Range
(dBs)
(LSBs)
Option3
AD7886JD
0
°C to +70°C
65
D-28
AD7886KD
0
°C to +70°C67
±2.0
D-28
AD7886JP
0
°C to +70°C
65
P-28A
2
AD7886KP
0
°C to +70°C67
±2.0
P-28A
2
AD7886BD
–40
°C to +85°C67
±2.0
D-28
AD7886TD
–55
°C to +125°C65
±2.0
D-28
NOTES
1Contact your sales office for availability of AD7886BD, AD7886TD and 1 MHz version.
2Analog Devices reserves the right to ship J-Leaded Ceramic Chip Carrier (JLCCC) in lieu of PLCC packages.
3D = Ceramic DIP; P = Plastic Leaded Chip Carrier.
PIN FUNCTION DESCRIPTION
DIP Pin
Number
Mnemonic
Description
Power Supply
10 & 19
VDD
Positive Power Supply, +5 V
± 5%. Both V
DD pins must be tied together.
15 & 24
VSS
Negative Power Supply, –5 V
± 5%. Both V
SS pins must be tied together.
16 & 23
AGND
Analog Ground. Both AGND pins must be tied together.
5
DGND
Digital Ground.
Analog and Reference Inputs
17 & 18
VIN
Analog Inputs, VIN1 and VIN2. The part can be pin strapped for any one of three analog input ranges;
Range
Pin Strap
Signal Input
0 V to 5 V
Connect VIN2 to VIN1
VIN1 & VIN2
0 V to 10 V
Connect VIN2 to GND
VIN1
±5 V
Connect VIN2 to +5 V
VIN1
20
+5REF
+5 V Reference input. This input is used in conjunction with SUM and VREF inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
21
SUM
Summing Point. This input is used in conjunction with +5REF and VREF inputs to scale an external
+5 V reference to –3.5 V, the required reference for the part (see Figure 2).
22
VREF
Voltage Reference Input. The AD7886 is specified with VREF = –3.5 V.
Interface and Control
1–4,
DB7–DB4
Three-state data outputs.
6–9,
DB3–DB0
These outputs are controlled by
CS and RD. DB11 is the Most Significant Bit (MSB).
25–28
DB11–DB8
11
BUSY
BUSY Output indicates converter status. BUSY is low during conversion.
12
CS
Chip Select Input. The device is selected when this input is low.
13
RD
Read Input. This active low signal, in conjunction with
CS, is used to enable the output data three-state
drivers.
14
CONVST
Conversion Start Input. This input is used to start conversion.
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