參數(shù)資料
型號： AD7890ANZ-2
廠商： Analog Devices Inc
文件頁數(shù)： 9/28頁
文件大?。?/td> 0K
描述： IC DAS 12BIT 8CH 24-DIP
標準包裝： 15
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 117k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 5V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應商設備封裝： 24-PDIP
包裝： 管件
AD7890
Rev. C | Page 17 of 28
SERIAL INTERFACE
The AD7890’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers, and digital signal processors.
A serial read to the AD7890 accesses data from the output
register via the DATA OUT line. A serial write to the AD7890
writes data to the control register via the DATA IN line.
Two different modes of operation are available, optimized for
different types of interface where the AD7890 can act either as
master in the system (it provides the serial clock and data
framing signal) or acts as slave (an external serial clock and
framing signal can be provided to the AD7890). The former is
self-clocking mode while the latter is external clocking mode.
SELF-CLOCKING MODE
The AD7890 is configured for its self-clocking mode by tying
the SMODE pin of the device to a logic low. In this mode, the
AD7890 provides the serial clock signal and the serial data
framing signal used for the transfer of data from the AD7890.
This self-clocking mode can be used with processors that allow
an external device to clock their serial port, including most
digital signal processors.
Read Operation
Figure 10 shows a timing diagram for reading from the AD7890
in the self-clocking mode. At the end of conversion, RFS goes
low and the serial clock (SCLK) and serial data (DATA OUT)
outputs become active. Sixteen bits of data are transmitted with
one leading zero, followed by the three address bits of the
control register, followed by the 12-bit conversion result starting
with the MSB. Serial data is clocked out of the device on the
rising edge of SCLK and is valid on the falling edge of SCLK.
The RFS output remains low for the duration of the 16 clock
cycles. On the 16th rising edge of SCLK, the RFS output is driven
high and DATA OUT is disabled.
RFS (O)
SCLK (O)
DATA OUT (O)
THREE-STATE
t2
t1
t3
t4
t5
t7
t6
THREE-STATE
LEADING
ZERO
DB0
DB10
DB11
A2
A1
A0
NOTES:
1. (I) SIGNIFIES AN INPUT.
2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
01
35
7-
0
10
Figure 10. Self-Clocking (Master) Mode Output Register Read
TFS (I)
SCLK (O)
DATA IN (I)
NOTES:
1. (I) SIGNIFIES AN INPUT.
2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
t8
t9
t10
t11
t3
t4
t12
A2
A1
A0
CONV
STBY
DON’T
CARE
DON’T
CARE
DON’T
CARE
01
35
7-
01
1
Figure 11. Self-Clocking (Master) Mode Control Register Write
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